be placed externally between GH and SH or GL and GND to protect the device from this type of transient. The

diode must be placed as close to the device pins as possible in order to be effective.

Low ESR bypass capacitors from BST to SH and from GVDD to GND are essential for proper operation of the

gate driver device. The capacitor should be located at the leads of the device to minimize series inductance.

The peak currents from GL and GH can be quite large. Any series inductance with the bypass capacitor causes

voltage ringing at the leads of the device which must be avoided for reliable operation.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Section 7.3.1 for more information on UVLO

operation mode. In normal mode, when the VGVDD and VBST–SH are above UVLO threshold, the output stage is

dependent on the states of the IN and SD pin. The outputs GH and GL will be low if input state is floating.

Table 7-3. Input/Output Logic in Normal Mode of Operation

SD

IN

GH(1)

GL(2)

L

L

L

L

L

H

L

L

H

L

L

H

H

H

H

L

Floating

Floating

L

L

(1)

GH is measured with respect to SH.

(2)

GL is measured with respect to GND.

8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

To operate power MOSFETs at high switching frequencies and to reduce associated switching losses, a powerful

gate driver is employed between the PWM output of controller and the gates of the power semiconductor

devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the

gates of the switching devices. With the advent of digital power, this situation is often encountered because

the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power

switch. Level-shift circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to

fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN

and PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack

level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate

drivers can also minimize the effect of high-frequency switching noise by being placed physically close to the

power switch. Additionally, gate drivers can drive gate-drive transformers and control floating power-device

gates, reducing the controller's power dissipation and thermal stress by moving the gate-charge power losses

into the driver.

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LM2104

SNVSCH8A – SEPTEMBER 2023 – REVISED OCTOBER 2023

Copyright © 2023 Texas Instruments Incorporated

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