8.2.3 Application Curves

Figure 8-2 shows the GL fall time and GH rise time as well as the propagation delays for both GL and GH when

the input IN transitions from low to high. Likewise, Figure 8-3 shows the GL rise time and GH fall time as well as

the propagation delays for both GL and GH when the input IN transitions from high to low. Each channel (IN, SD,

GH, and GL) is labeled and displayed on the left hand of the waveforms.

The testing condition: load capacitance is 1 nF, gate resistor is 4 Ω, VDD = 12 V, fSW = 50 kHz.

CL = 1 nF

RG = 4 Ω

VDD = 12 V

fSW = 50 kHz

Figure 8-2. GL Fall Time, GH Rise Time and

Propagation Delays

CL = 1 nF

RG = 4 Ω

VDD = 12 V

fSW = 50 kHz

Figure 8-3. GL Rise Time, GH Fall Time and

Propagation Delays

9 Power Supply Recommendations

The recommended bias supply voltage range for LM2104 is from 9 V to 18 V. The lower end of this range is

governed by the internal undervoltage lockout (UVLO) protection feature of the VGVDD supply circuit blocks. The

upper end of this range is driven by the 18-V recommended maximum voltage rating of the GVDD pin. It is

recommened that the voltage on GVDD pin is lower than the maximum recommended voltage to account for

transient voltage spikes.

The UVLO protection feature also involves a hysteresis function. This means that once the device is operating

in normal mode, if the VGVDD voltage drops, the device continues to operate in normal mode as long as the

voltage drop does not exceed the hysteresis specification, VDDHYS. If the voltage drop is more than hysteresis

specification, the device shuts down. Therefore, while operating at or near the 9-V range, the voltage ripple on

the auxiliary power supply output must be smaller than the hysteresis specification of LM2104 to avoid triggering

device-shutdown.

A local bypass capacitor must be placed between the GVDD and GND pins and this capacitor must be

located as close to the device as possible. A low-ESR, ceramic surface mount capacitor is recommended. TI

recommends using two capacitors across GVDD and GND: a low capacitance ceramic surface-mount capacitor

for high-frequency filtering placed very close to GVDD and GND pins, and another high capacitance value

surface-mount capacitor for IC bias requirements. In a similar manner, the current pulses delivered by the GH

pin are sourced from the BST pin. Therefore, a local decoupling capacitor is recommended between the BST

and SH pins.

LM2104

SNVSCH8A – SEPTEMBER 2023 – REVISED OCTOBER 2023

www.ti.com

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