PQC = VGVDD × IGVDD + (VGVDD – VF) × IBST = 12V × 0.43mA + (12V – 1V) × 0.15mA = 6.8mW

(11)

2. Level-shifter losses, PIBSTS, due high-side leakage current IBSTS is shown in Equation 12.

PIBSTS = VBST × IBSTS × D = 72V × 0.033mA × 0.95 = 2.26mW

(12)

where

• D is the high-side switch duty cycle

3. Dynamic losses, PQG1&2, due to the FETs gate charge QG as shown in Equation 13.

PQG1&2=2×VGVDD×QG×fSW× RGD_R

RGD_R+RGATE+RGFET_INT= 2×12V×17nC×50kHz× 5.25Ω

5.25Ω+4.7Ω+2.2Ω

=8.8mW

(13)

where

• QG = Total FETs gate charge

• fSW = Switching frequency

• RGD_R = Average value of pullup and pulldown resistor

• RGATE = External gate drive resistor

• RGFET_INT = Internal FETs gate resistor

4. Level-shifter dynamic losses, PLS, during high-side switching due to required level-shifter charge on each

switching cycle. For this example it is assumed that value of parasitic charge QP is 2.5 nC, as shown in

Equation 14.

PLS = VBST × QP × fSW = 72V × 2.5nC × 50kHz = 9mW

(14)

In this example, the sum of all the losses is 27 mW as a total gate driver loss. For gate drivers that include

bootstrap diode, one should also estimate losses in the bootstrap diode. Diode forward conduction loss is

computed as product of average forward voltage drop and average forward current.

Equation 15 estimates the maximum allowable power loss of the device for a given ambient temperature.

PMAX=TJ−TARθJA

(15)

where

• PMAX = Maximum allowed power dissipation in the gate driver device

• TJ = Junction temperature

• TA = Ambient temperature

• RθJA = Junction-to-ambient thermal resistance

The thermal metrics for the driver package is summarized in the Thermal Information table of the data sheet.

For detailed information regarding the thermal information table, refer to the Texas Instruments application note

entitled Semiconductor and IC Package Thermal Metrics.

www.ti.com

LM2104

SNVSCH8A – SEPTEMBER 2023 – REVISED OCTOBER 2023

Copyright © 2023 Texas Instruments Incorporated

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