8.2.1 Design Requirements

Table 8-1 lists the design parameters of the LM2005.

Table 8-1. Design Example

PARAMETER

VALUE

Gate Driver

LM2005

MOSFET

CSD19534KCS

VDD

12 V

QG

17 nC

fSW

50 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Select Bootstrap and GVDD Capacitor

The bootstrap capacitor must maintain the VBST-SH voltage above the UVLO threshold for normal operation.

Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1.

∆VBST =VGVDD−VDH−VBSTL=12V−2.1V−8.05V=1.85V

(1)

where

• VGVDD = Supply voltage of the gate drive IC

• VDH = Bootstrap diode forward voltage drop

• VBSTL = BST falling threshold (VBSTR(max) - VBSTHYS)

Then, the total charge needed per switching cycle is estimated by Equation 2.

QTOTAL=QG+IBSTS×DMAXfSW+IBSTfSW=17nC+33.3μA× 0.9550kHz+150μA50kHz=20nC

(2)

where

• QG = Total MOSFET gate charge

• IBSTS = BST to VSS leakage current

• DMax = Converter maximum duty cycle

• IBST = BST quiescent current

Next, use Equation 3 to estimate the minimum bootstrap capacitor value.

CBOOT MIN =QTOTAL

∆VBST =20nC1.85V=10.8nF

(3)

In practice, the value of the CBoot capacitor must be greater than calculated to allow for situations where the

power stage may skip pulse due to load transients. Equation 4 can be used to estimate the recommended

bootstrap capacitance based on the maximum bootstrap voltage ripple desired for a specific application.

CBOOT > QTOTAL

∆VBST_RIPPLE

(4)

where

• ∆VBST_RIPPLE = Maximum allowable voltage drop across the bypass capacitor based on system requirements

TI recommends having enough margins and to place the bootstrap capacitor as close to the BST and SH pins as

possible.

CBOOT = 100 nF

(5)

LM2005

SNVSCB6B – FEBRUARY 2023 – REVISED SEPTEMBER 2023

www.ti.com

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