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INA849 Datasheet(PDF) 32 Page - Texas Instruments |
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INA849 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 42 page  9.4.2 Layout Example GND GND GND IN– 4 IN+ 1 2 3 FDA_IN+ OUT– OUT+ 9 FDA_IN– 12 11 10 PAD R2 GND VIN+ R1 GND C4 C2 C7 C6 VOCM ADC_INP ADC_INN Use ground pours for shielding the input signal pairs Place bypass capacitors as close to IC as possible R3 R4 C10 Consider utilizing thermal vias for heatsinking Cutouts on ground planes underneath input pins can reduce stray capacitance, for better phase margin C8 C9 GND VIN+ VIN VS+ R2 R1 C2 C5 PGA855 ADC C6 C7 INP INN C10 R3 R4 OUT+ OUT VCM C9 C8 Connect feedback capacitors between OUTx and FDA_INx (optional) A<2:0> DGND VIN A2 A0 C1 GND LVSS VS C3 C5 VS+ LVDD Optional noise filtering capacitors LVDD C4 C1 LVSS VS C3 Figure 9-12. Example Schematic and Associated PCB Layout PGA855 SBOSAE0B – APRIL 2023 – REVISED SEPTEMBER 2023 www.ti.com 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: PGA855 |
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