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9.2 Typical Applications

9.2.1 ADS127L11 and ADS127L21, 24-Bit, Delta-Sigma ADC Driver Circuit

The application circuit in Figure 9-6 shows a schematic for a 24-bit wide-bandwidth, delta-sigma ADC. The

ADS127Lx1 ADC offers two digital filters to optimize ac applications (wideband filter) or dc applications (sinc4

filter). Table 9-2 and Table 9-3 show measurement results in both filter settings. For a detailed design procedure

to operate the ADS127Lx1 ADC, see the ADS127Lx1EVM-PDK evaluation module user's guide.

–

OUT+

IN+

OUT

VOCM

5 k

ADS127L11

1x Input Range

INP

INN

FDA_IN

FDA_IN+

PGA855

–

VIN+

VIN

VO = G × (VIN+

VIN )

Gain Network

DGND

VREF

AVDD

CFB

25 pF

CFB

25 pF

RFIL

47.4

RFIL

47.4

CDIFF

560 pF

CCM

51 pF

CCM

51 pF

1 k

1000 pF

ADS127L11

VCM Pin

VS+

15 V

100 nF

5 V

15 V

100 nF

LVDD

LVSS

AVSS

4.096 V

RFIL_Optional

CIN_DIFF

10 ×

CIN_CM

1 ×

CIN_CM

1 ×

100 nF

Figure 9-6. Driving the ADS127Lx1 Delta-Sigma ADC

9.2.1.1 Design Requirements

The design requirements for the application driving the ADS127Lx1 ADC are listed in the following table.

Table 9-1. Design Parameters

PARAMETER

VALUE

Differential-to-differential conversion

VINDIFF to VOUTDIFF

Supply voltages

VS± = ±15 V, VLVDD = 5 V, VLVSS = GND, VREF = 4.096 V

Full-scale range of ADC

FSR = ± 4.096 V

Data rate of ADC

fDATA = 187.5 kSPS

ADC filter configuration

(1) High-speed mode, Sinc4 filter, OSR = 64

(2) High-speed mode, Wideband filter, OSR = 64

PGA gain

See Table 9-2 and Table 9-3

Signal frequency

Tested at fIN = 1 kHz

RC kickback filter(1)

RFIL = 47.4 Ω, CDIFF = 560 pF, CCM = 51 pF

(1)

Consider a trade-off between THD, frequency response, and drift. The differential current drift

into the ADC can interact with the filter resistors and result in higher drift errors. However, lower

resistance degrades the phase margin of the PGA855. For low drift applications, keep RFIL < 50 Ω.

PGA855

SBOSAE0B – APRIL 2023 – REVISED SEPTEMBER 2023

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