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9.2.2 ADS8900B 20-Bit SAR ADC Driver Circuit

The application circuit in Figure 9-9 shows the schematic for the 20-bit, precision, 1-MSPS, successive

approximation register (SAR), analog-to-digital converter (ADC). This circuit is used to measure the driving

capability of the PGA855 with the ADS8900B ADC. The circuit accepts single-ended or differential input signals.

The PGA855 operates with independent input and output power supplies. In this example, ±15

‑V power supplies

are used for the input section, and a 5.3

‑V power supply for the output section.

To reduce extrinsic voltage supply noise, the ADC portion of the circuit uses the TPS7A4700, a low-noise,

4-μVRMS LDO voltage regulator, to generate a unipolar 5.3

‑V ADC supply rail and the PGA855 output stage

supply is powered by the same 5.3-V ADC supply. The 5.3

‑V output supply operation prevents overloading

the ADC inputs during PGA overdrive conditions. The REF5050 is selected as a voltage reference; this is a

low-noise, low-drift, precision 5-V reference connected to the ADS8900B REFIN pin.

–

OUT+

IN–

IN+

OUT–

VOCM

ADS8900B

SAR ADC

INP

INN

FDA_IN–

FDA_IN+

PGA855

–

VIN+

VIN

Gain Network

DGND

REFIN

AVDD

CFB

200pF

CFB

200pF

RFIL

47.4

RFIL

47.4

CDIFF

560pF

CCM

51pF

CCM

51pF

10nF

VS+

+15V

100nF

+5.3V

–15V

100nF

LVDD

LVSS

AVSS

REF5050

+5.0V

Reference

RIN_FIL

CIN_DIFF

10x

CIN_CM

VS–

1µF

10µF

18.7k

20.7k

REF5050

+5.0V

Reference

Figure 9-9. Driving the SAR ADC ADS8900B

9.2.2.1 Design Requirements

The design requirements for the application driving the ADS8900B ADC are listed in the following table.

Table 9-4. Design Parameters

PARAMETER

VALUE

Supply voltages

VS± = ±15 V, VLVDD = 5.3 V, VLVSS = GND, VREF = 5 V

Full-scale range of ADC

FSR = ±5 V

Sampling rate of ADC

fSAMPLE = 1 MSPS

PGA gain

See Table Table 9-5

Input signal amplitude

See Table Table 9-5

Signal frequency

Tested at fIN = 1 kHz

RC kickback filter

RFIL = 47.4 Ω, CDIFF = 560 pF, CCM = 51 pF

9.2.2.2 Detailed Design Procedure

The ADS8900B requires an input common-mode voltage within the range of VREF / 2 ±100 mV. The PGA855

VOCM pin is set to a nominal voltage of approximately 2.58 V. The VOCM voltage is purposely set to a voltage

slightly greater than VREF / 2 to maximize the output voltage swing range of the PGA855, while allowing margin

for the VOCM offset voltage error and drift variation. The VOCM voltage is generated by feeding the REF5050

reference through an 18.7 kΩ- to 0 kΩ voltage divider implemented with 0.1% tolerance resistors. An additional

RC filter with R = 1 kΩ, C = 10 nF is used in close proximity to the VOCM pin as shown on Figure 9-9.

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PGA855

SBOSAE0B – APRIL 2023 – REVISED SEPTEMBER 2023

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