ATMEGA48 datasheet(155/374 Pages) ATMEL

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155

2545J–AVR–12/06

ATmega48/88/168

Table 16-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on

page 148 for more details.

Table 16-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on

page 148 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 1:0 – WGM21:0: Waveform Generation Mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 16-8. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see ”Modes of Operation” on page 145).

Table 16-6.

Compare Output Mode, Fast PWM Mode(1)

COM2B1

COM2B0

Description

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match, set OC2B at BOTTOM,

(non-inverting mode)

Set OC2B on Compare Match, clear OC2B at BOTTOM,

(invertiing mode)

Table 16-7.

Compare Output Mode, Phase Correct PWM Mode

(1)

COM2B1

COM2B0

Description

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match when up-counting. Set OC2B on

Compare Match when down-counting.

Set OC2B on Compare Match when up-counting. Clear OC2B on

Compare Match when down-counting.

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