ATMEGA649 datasheet(180/375 Pages) ATMEL

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ATmega329/3290/649/6490

2552H–AVR–11/06

• Bit 4 – FEn: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when

received. I.e., when the first stop bit of the next character in the receive buffer is zero.

This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop

bit of received data is one. Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the

receive buffer is full (two characters), it is a new character waiting in the Receive Shift

is read. Always set this bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received

and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the

receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using

synchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-

tively doubling the transfer rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCMn bit is writ-

ten to one, all the incoming frames received by the USART Receiver that do not contain

address information will be ignored. The Transmitter is unaffected by the MPCMn set-

ting. For more detailed information see “Multi-processor Communication Mode” on page

178.

UCSRnB – USART Control

and Status Register n B

• Bit 7 – RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete

interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt

Flag in SREG is written to one and the RXCn bit in UCSRnA is set.

• Bit 6 – TXCIEn: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete

interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt

Flag in SREG is written to one and the TXCn bit in UCSRnA is set.

• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty

interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt

Flag in SREG is written to one and the UDREn bit in UCSRnA is set.

• Bit 4 – RXEN0: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normal

port operation for the RxD pin when enabled. Disabling the Receiver will flush the

receive buffer invalidating the FEn, DORn, and UPEn Flags.

Bit

321

RXCIEn

TXCIEn

UDRIEn

RXENn

TXENn

UCSZn2

RXB8n

TXB8n

UCSRnB

Read/Write

R/W

Initial Value

ATMEGA649 Datasheet(PDF) 180 Page - ATMEL Corporation

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