ATMEGA649 datasheet(57/375 Pages) ATMEL

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ATmega329/3290/649/6490

2552H–AVR–11/06

EIFR – External Interrupt Flag

• Bit 7 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT30..24 pin triggers an interrupt request, PCIF3

becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

This bit is reserved bit in ATmega329/649 and will always be read as zero.

• Bit 6 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2

becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

This bit is reserved bit in ATmega329/649 and will always be read as zero.

• Bit 5 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1

becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

• Bit 4 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0

becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it. This flag is always cleared when INT0 is configured as a level interrupt.

PCMSK3 – Pin Change Mask

(1)

• Bit 6:0 – PCINT30..24: Pin Change Enable Mask 30..24

Each PCINT30..24-bit selects whether pin change interrupt is enabled on the corre-

sponding I/O pin. If PCINT30..24 is set and the PCIE3 bit in EIMSK is set, pin change

interrupt is enabled on the corresponding I/O pin. If PCINT30..24 is cleared, pin change

interrupt on the corresponding I/O pin is disabled.

Bit

654

0x1C (0x3C)

PCIF3

PCIF2

PCIF1

PCIF0

–

INTF0

EIFR

Read/Write

R/W

Initial Value

Bit

654

321

(0x73)

–

PCINT30

PCINT29

PCINT28

PCINT27

PCINT26

PCINT25

PCINT24

PCMSK3

Read/Write

R/W

Initial Value

ATMEGA649 Datasheet(PDF) 57 Page - ATMEL Corporation

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