ATMEGA649 datasheet(187/375 Pages) ATMEL

187 / 375 page

187

ATmega329/3290/649/6490

2552H–AVR–11/06

USI – Universal Serial

Interface

The Universal Serial Interface, or USI, provides the basic hardware resources needed

for serial communication. Combined with a minimum of control software, the USI allows

significantly higher transfer rates and uses less code space than solutions based on

software only. Interrupts are included to minimize the processor load. The main features

of the USI are:

• Two-wire Synchronous Data Transfer (Master or Slave)

• Three-wire Synchronous Data Transfer (Master or Slave)

• Data Received Interrupt

• Wake up from Idle Mode

• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

• Two-wire Start Condition Detector with Interrupt Capability

Overview

A simplified block diagram of the USI is shown on Figure 77. For the actual placement of

I/O pins, refer to “Pinout ATmega3290/6490” on page 2 and “Pinout ATmega329/649”

on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in

bold. The device-specific I/O Register and bit locations are listed in the “USI Register

Descriptions” on page 195.

Figure 77. Universal Serial Interface, Block Diagram

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming

and outgoing data. The register has no buffering so the data must be read as quickly as

possible to ensure that no data is lost. The most significant bit is connected to one of two

output pins depending of the wire mode configuration. A transparent latch is inserted

between the Serial Register Output and output pin, which delays the change of data out-

put to the opposite clock edge of the data input sampling. The serial input is always

sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an

overflow interrupt. Both the Serial Register and the counter are clocked simultaneously

by the same clock source. This allows the counter to count the number of bits received

or transmitted and generate an interrupt when the transfer is complete. Note that when

an external clock source is selected the counter counts both clock edges. In this case

the counter counts the number of edges, and not the number of bits. The clock can be

Two-wire Clock

Control Unit

(Output only)

DI/SDA

(Input/Open Drain)

USCK/SCL

(Input/Open Drain)

4-bit Counter

USIDR

USISR

USICR

CLOCK

HOLD

TIM0 COMP

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