ATMEGA649 datasheet(203/375 Pages) ATMEL

203 / 375 page

203

ATmega329/3290/649/6490

2552H–AVR–11/06

Analog to Digital

Converter

Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock)

• Up to 76.9 kSPS at Maximum Resolution (200 kHz ADC clock)

• Eight Multiplexed Single Ended Input Channels

• Optional Left Adjustment for ADC Result Readout

• 0 - V

CC ADC Input Voltage Range

• Selectable 1.1V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The ATmega329/3290/649/6490 features a 10-bit successive approximation ADC. The

ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended

voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer

to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the

ADC is held at a constant level during conversion. A block diagram of the ADC is shown

in Figure 84.

The ADC has a separate analog supply voltage pin, AVCC. AV

CC must not differ more

than ± 0.3V from V

CC. See the paragraph “ADC Noise Canceler” on page 209 on how to

connect this pin.

Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The volt-

age reference may be externally decoupled at the AREF pin by a capacitor for better

noise performance.

The PRADC, in “Power Reduction Register - PRR” on page 35 must be written to zero

to enable the ADC module.

ATMEGA649 Datasheet(PDF) 203 Page - ATMEL Corporation