EFM32GG11 datasheet(77/261 Pages) SILABS

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EBI Address Latch Enable Output Timing

Timing applies to multiplexed addressing modes D8A24ALE and D16A16ALE for both polarities. All numbers are based on route loca-

tions 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of

IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.

Table 4.37. EBI Address Latch Enable Output Timing

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output hold time, from trail-

ing EBI_ALE edge to

EBI_AD invalid1 2

tOH_ALEn

IOVDD ≥ 1.62 V

-22 +

(ADDR-

HOLD *

tHFCOR-

ECLK)

—

IOVDD ≥ 3.0 V

-11 +

(ADDR-

HOLD *

tHFCOR-

ECLK)

—

Output setup time, from

EBI_AD valid to leading

EBI_ALE edge

tOSU_ALEn

IOVDD ≥ 1.62 V

-12

—

IOVDD ≥ 3.0 V

-9

—

EBI_ALEn pulse width1

tWIDTH_ALEn

IOVDD ≥ 1.62 V

-4 +

((ADDR-

SETUP +

1) *

t{}HFCOR-

ECLK{})

—

IOVDD ≥ 3.0 V

-3 +

((ADDR-

SETUP +

1) *

t{}HFCOR-

ECLK{})

—

Note:

1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge of

EBI_ALEn can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length of

tOSU_ALEn by tHFCORECLK - 1/2 * tHFCLKNODIV.

2. The figure shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state

instead of via the ADDRHOLD state.

EFM32GG11 Family Data Sheet

Electrical Specifications

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