EFM32GG11 datasheet(87/261 Pages) SILABS

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4.1.27 Serial Data I/O Host Controller (SDIO)

SDIO DS Mode Timing

Timing is specified at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 6, all other GPIO set to 6, DRIVES-

TRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 40

pF on all pins.

Table 4.46. SDIO DS Mode Timing (Location 0)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Clock frequency during data

transfer

FSD_CLK

Using HFRCO, AUXHFRCO, or

USHFRCO

—

MHz

Using HFXO

—

20.5

MHz

Clock low time

tWL

Using HFRCO, AUXHFRCO, or

USHFRCO

19.6

—

Using HFXO

19.1

—

Clock high time

tWH

Using HFRCO, AUXHFRCO, or

USHFRCO

19.6

—

Using HFXO

19.1

—

Clock rise time

1.4

—

4.9

Clock fall time

1.2

—

4.0

Input setup time, CMD,

DAT[0:3] valid to SD_CLK

tISU

—

Input hold time, SD_CLK to

CMD, DAT[0:3] change

tIH

—

Output delay time, SD_CLK

to CMD, DAT[0:3] valid

tODLY

—

18.6

Output hold time, SD_CLK to

CMD, DAT[0:3] change

tOH

—

Table 4.47. SDIO DS Mode Timing (Location 1)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Clock frequency during data

transfer

FSD_CLK

Using HFRCO, AUXHFRCO, or

USHFRCO

—

MHz

Using HFXO

—

13.5

MHz

Clock low time

tWL

Using HFRCO, AUXHFRCO, or

USHFRCO

32.3

—

Using HFXO

29.2

—

Clock high time

tWH

Using HFRCO, AUXHFRCO, or

USHFRCO

32.3

—

Using HFXO

29.2

—

Clock rise time

1.4

—

4.9

Clock fall time

1.2

—

4.0

EFM32GG11 Family Data Sheet

Electrical Specifications

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