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EFM32GG11 Datasheet(PDF) 82 Page - Silicon Laboratories |
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EFM32GG11 Datasheet(HTML) 82 Page - Silicon Laboratories |
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82 / 261 page ![]() EBI Read Enable Timing Requirements Timing applies to both EBI_REn and EBI_NANDREn for all addressing modes and both polarities. All numbers are based on route loca- tions 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6. Table 4.40. EBI Read Enable Timing Requirements Parameter Symbol Test Condition Min Typ Max Unit Setup time, from EBI_AD valid to trailing EBI_REn edge tSU_REn IOVDD ≥ 1.62 V 55 — — ns IOVDD ≥ 3.0 V 36 — — ns Hold time, from trailing EBI_REn edge to EBI_AD in- valid tH_REn IOVDD ≥ 1.62 V -9 — — ns EBI_A[N-1:0] EBI_AD[15:0] ADDR[N:1] RDSETUP (0, 1, 2, ...) EBI_CSn EBI_REn RDSTRB (1, 2, 3, ...) RDHOLD (0, 1, 2, ...) tSU_REn tH_REn Z Z DATA[15:0] Z Figure 4.7. EBI Read Enable Timing Requirements EFM32GG11 Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.2 | 82 |
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