VT1705 datasheet(13/99 Pages) ETC

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Data Sheet

VT1705 High Definition Audio Codec

7 High Definition Audio Link Protocol

7.1 Link Signaling

The link protocol defines the digital serial interface that connects High Definition Audio codec to the audio

controller, and is not compatible with the previous AC97 protocol. The link is controller synchronous,

based on a fixed 24MHz BITCLK and is purely isochronous without any flow control.

Figure 3 – High Definition Audio Link Conceptual View

7.2 Signal Definitions

Table 3 – High Definition Audio Link Signal Description

Signal Name

Source

Type

Description

BITCLK

Controller

24 MHz Clock

SYNC

Controller

Global 48 kHz Frame Sync and Outbound Tag Signal.

SDO

Controller

Bussed Serial Data Output from Controller.

SDI

Codec &

controller

Point-to-point Serial Data. The controller has a weak pull

down.

RESETN

Controller

Global Active Low Reset Signal.

BITCLK is the 24 MHz clock sourced from the controller and connecting to all codec on the link.

SYNC marks input and output frame boundaries (Frame Sync) as well as identifying outbound data

streams (stream tags). SYNC is always sourced from the controller and connects to all codec on the link.

SDO is driven by the controller to all codec on the link. Compared with AC97, the SDO is double pumped

with respect to both rising and falling edges of BITCLK in order to increase the bandwidth required for

High Definition Audio link.

SDI is a point-to-point data signal driven by the codec to the controller. Because the bandwidth

requirement is not that high compared with SDO, the data is single pumped with respect to only the rising

edge of BITCLK. The controller is required to implement weak pull-down on all SDI signals.

RESETN is sourced from the controller and connects to all codec on the link. Assertion of RESETN results

in all link interface logic being reset to Default power on state.

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