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LT8277 Datasheet(PDF) 20 Page - Analog Devices |
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LT8277 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 31 page ![]() Data Sheet LT8277 analog.com Rev 0 20 of 31 Loop Compensation To stabilize the control loop formed by the LT8277 and the associated power stage, connect an RC network between the VC pin and ground. For many low-frequency applications, a 4.7nF capacitor and 10k resistor will suffice. If the above values do not satisfy stability requirements, first try adjusting the value of the capacitor. If the response is stable but ringy, try adjusting the value of the resistor. If neither of these works, consider using a lower programmed current limit (if possible), changing the value of the output capacitor, or changing the value of the inductor. Programming the Switching Frequency To program the switching frequency for the LT8277, connect a single resistor between the RT pin and the ground. To select a resistor, see Table 10. Note that for the same component values, increasing switching frequency will reduce input and output voltage ripple and reduce inductor current ripple, but it can also decrease efficiency. To synchronize LT8277 to an external clock, drive the SYNC/SPRD pin with that clock. Choose RT such that the programmed switching frequency is within ±15% of the external clock frequency. Like all switching converters, the LT8277 can create electromagnetic interference (EMI). One way to reduce the EMI emitted by a switching converter is to use spread spectrum frequency modulation (SSFM). To enable internal SSFM, tie the SYNC/SPRD pin to INTVCC. Table 10. Selected RT values and Switching Frequency FSW (kHz) RT (kΩ) 100 523 200 191 250 143 300 115 400 82.5 500 63.4 1000 28.0 2000 11.0 Soft-Start and PGOOD Reporting To reduce stress seen by external components, LT8277 uses a soft-start. When switching begins, either after power- on or when recovering from a fault, the output voltage target and switching frequency fall considerably below their nominal values. As the startup proceeds, both constraints relax. The duration of the foldback depends on RT. The duration of a soft-start can become lengthy for low switching frequency applications. The SPI interface provides a bit to speed up soft-start, decreasing its duration to 25% of the default soft-start time set by RT. During soft-start, LT8277 inhibits the PGOOD signal to allow the part to reach a steady state. However, once soft- start is complete, the PGOOD pin will be asserted whenever the output voltage is within 5% of the value programmed using the SPI port. The PGOOD pin is an active-high open-drain signal, and using a resistive pull-up to VIN or INTVCC is recommended to prevent errant assertions of the PGOOD signal while the part is unpowered. If the output voltage exceeds the programmed value by around 5%, switching will stop, irrespective of the voltage at VC. If the output falls to less than 30% of the value programmed using the SPI port, switching stops. After a brief cooldown period, the part will attempt to restart as if power had just been applied. |
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