Table 6-11. TI Test Mode Control Register (Channel register base + Offset = 0x04) (continued)

Bit

Field

Type

Reset

Description

2

TI test mode

R/W

0x0

Set TI test mode:

0: test mode is enabled

1: test mode is disabled. Must be set to "1" for normal operation.

Table 6-12. PD Override Register (Channel register base + Offset = 0x05)

Bit

Field

Type

Reset

Description

7

device_en_override

R/W

0x0

Enable power down overrides through SMBus/I2C

0: Manual override disabled

1: Manual override enabled

6-0

device_en

R/W

0x111111

Manual power down of redriver various blocks of a channel –

gated by device_en_override = 1

111111: All blocks in the channel are enabled

000000: All blocks in the channel are disabled

Table 6-13. Bias Register (Channel register base + Offset = 0x06)

Bit

Field

Type

Reset

Description

5-3

Bias current

R/W

0x100

Control bias current

Set 001 for best performance

7,6,2-0

Reserved

R/W

0x00000

Reserved

6.5.3 SMBus/I2C Primary Mode Configuration (EEPROM Self Load)

The TDP2004 can also be configured by reading from EEPROM. To enter into this mode MODE pin must be

set to L1. The EEPROM load operation only happens once after the device's initial power-up. If the TDP2004

is configured for SMBus Primary mode, then it will remain in the SMBus IDLE state until the READ_EN_N pin

is asserted to LOW. After the READ_EN_N pin is driven LOW, theTDP2004 becomes an SMBus primary and

attempts to self-configure by reading the device settings stored in an external EEPROM (SMBus 8-bit address

0xA0). When the TDP2004 has finished reading from the EEPROM successfully, it will drive the DONEn pin

LOW. SMBus/I2C secondary operation is available in this mode before, during, or after EEPROM reading. Note:

during EEPROM reading, if the external SMBus/I2C primary wants to access TDP2004 registers, then it must

support arbitration.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

• EEPROM size of 2Kb (256 × 8-bit) is recommended.

• Set MODE = L1, configure for SMBus Primary mode.

• The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 3.3 V supply

• In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor.

The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus

capacitance of 10 pF.

Multiple TDP2004 can be cascaded to read from single EEPROM. Tie the READ_EN_N pin of the first device

low (GND) to automatically initiate EEPROM read at power up. DONEn of the first device can be fed into

READ_EN_N of the next device with 4.7k pull-up resistors. Leave the DONEn pin of the final device floating, or

connect the pin to a micro-controller input to monitor the completion of the final EEPROM read.

TDP2004

SNLS745 – NOVEMBER 2023

www.ti.com

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