TDP2004 datasheet(9/29 Pages) TI1

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5.7 SMBUS/I2C Timing Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tLOW

LOW period of the SCL clock

1.3

µs

THIGH

HIGH period of the SCL clock

0.6

µs

tSU-STA

Set-up time for a repeated START

condition

0.6

µs

tHD-DAT

Data hold time

µs

TSU-DAT

Data setup time

0.1

µs

Rise time of both SDA and SCL

signals

Pull-up resistor = 4.7 kΩ, Cb = 10 pF

120

Fall time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10 pF

tSU-STO

Set-up time for STOP condition

0.6

µs

tBUF

Bus free time between a STOP and

START condition

1.3

µs

tVD-DAT

Data valid time

0.9

µs

tVD-ACK

Data valid acknowledge time

0.9

µs

Capacitive load for each bus line

400

Primary Mode

fSCL-M

SCL clock frequency

303

kHz

tLOW-M

SCL low period

1.90

µs

THIGH-M

SCL high period

1.40

µs

tSU-STA-M

Set-up time for a repeated START

condition

µs

tHD-STA-M

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

1.5

µs

TSU-DAT-M

Data setup time

1.4

µs

tHD-DAT-M

Data hold time

0.5

µs

tR-M

Rise time of both SDA and SCL

signals

Pull-up resistor = 4.7 kΩ, Cb = 10 pF

120

TF-M

Fall time of both SDA and SCL signals Pull-up resistor = 4.7 kΩ, Cb = 10 pF

tSU-STO-M

Stop condition setup time

1.5

µs

EEPROM Timing

TEEPROM

EEPROM configuration load time

Time to assert DONEn after

READ_EN_N has been asserted.

7.5

TPOR

Time to first SMBus access

Power supply stable after initial ramp.

Includes initial power-on reset time.

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TDP2004

SNLS745 – NOVEMBER 2023

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