Table 4-1. Pin Functions (continued)

PIN

TYPE(1)

DESCRIPTION

NAME

NO.

MODE

25

I, 5-level

Sets device control configuration modes. 5-level IO pin as provided in Table 6-3. The

pin can be exercised at device power up or in normal operation mode.

L0: Pin mode – device control configuration is done solely by strap pins.

L1: SMBus/I2C Primary mode – device control configuration is read from external

EEPROM. When the TDP2004 has finished reading from the EEPROM successfully,

it will drive the DONEn pin LOW. SMBus/I2C secondary operation is available in this

mode before, during or after EEPROM reading. Note: during EEPROM reading if

the external SMBus/I2C primary wants to access TDP2004 registers it must support

arbitration.

L2: SMBus/I2C Secondary mode – device control configuration is done by an external

controller with SMBus/I2C primary.

L3 and L4 (Float): RESERVED – TI internal test modes.

EQ0 / ADDR0

23

I, 5-level

In Pin mode:

Sets receiver linear equalization (CTLE) boost for channels 0-3 as provided in Table

6-1. These pins are sampled at device power-up only.

In SMBus/I2C mode:

Sets SMBus / I2C secondary address as provided in Table 6-4. These pins are

sampled at device power-up only.

EQ1 / ADDR1

24

I, 5-level

GAIN / SDA

27

I, 5-level / I/O,

3.3 V

LVCMOS,

open drain

In Pin mode:

Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The

pin is sampled at device power-up only.

In SMBus/I2C mode:

3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /

I2C interface standard.

GND

1, 8, 11, 18,

21, 28, 31, 38,

EP

P

Ground reference for the device.

EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return

for the device. The EP should be connected to one or more ground planes through the

low resistance path. A via array provides a low impedance path to GND. The EP also

improves thermal dissipation.

PD

6

I, 3.3 V

LVCMOS

2-level logic controlling the operating state of the redriver. Active in all device control

modes. The pin has internal 1-MΩ weak pull-down resistor.

High: power down for channels 0-3

Low: power up, normal operation for channels 0-3

READ_EN_N

22

I, 3.3 V

LVCMOS

In SMBus/I2C Primary mode:

After device power up, when the pin is low, it initiates the SMBus / I2C Primary mode

EEPROM read function. When EEPROM read is complete (indicated by assertion

of DONEn low), this pin can be held low for normal device operation. During the

EEPROM load process the device’s signal path is disabled.

In SMBus/I2C Secondary and Pin modes:

In these modes the pin is not used. The pin can be left floating. The pin has internal

1-MΩ weak pull-down resistor.

RSVD

2

—

Reserved use for TI. The pin must be left floating (NC).

TEST / SCL

26

I, 5-level / I/O,

3.3 V

LVCMOS,

open drain

In Pin mode:

TI test mode. External 1 kΩ pull down resistor must be installed.

In SMBus/I2C mode:

3.3V SMBus/I2C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /

I2C interface standard.

RX0N

30

I

Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from

the pin to internal CM bias voltage. Channel 0.

RX0P

29

I

Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor

from the pin to internal CM bias voltage. Channel 0.

RX1N

33

I

Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from

the pin to internal CM bias voltage. Channel 1.

RX1P

32

I

Non-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor

from the pin to internal CM bias voltage. Channel 1.

RX2N

37

I

Inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from

the pin to internal CM bias voltage. Channel 2.

TDP2004

SNLS745 – NOVEMBER 2023

www.ti.com

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