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IR3084A Datasheet(PDF) 12 Page - International Rectifier |
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IR3084A Datasheet(HTML) 12 Page - International Rectifier |
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12 / 45 page  IR3084A Page 12 of 45 10/30/2006 IR3084A THEORY OF OPERATION Block Diagram 1.1V SET VR10 DAC VID7 + - EAOUT BIAS REGULATOR ERROR AMP + - + - + - SS DISCHARGE COMPARATOR IREGSET + - DISABLE START LATCH R S FAULT STARTUP NO CPU LATCHED IROSC IROSC IROSC IROSC IROSC IROSC IROSC IROSC IROSC 3.1V 6.9V + - VID SAMPLE DELAY COMPARATOR + - R VID4 VOSNS- NO CPU FAULT LATCH IROSC S VID0 VID1 VID2 VIDSEL VID3 VDAC VID FAULT CODE + - 1.3V VDRP AMP + ICHG 70uA 50% DUTY CYCLE 4.8V VCHG 3.85V I_OC_DISCHG 40uA R 850mV 1.3us BLANKING 9.9V FAULT LATCH VID6 VID5 100mV ROSC BUFFER AMP 80mV ISINK OC COMPARATOR 0.9V CURRENT SOURCE GENERATOR IOCSET RAMP GENERATOR DIGITAL TO ANALOG CONVERTER 750mV IOFFSET VID INPUT COMPARATORS (1 of 8 shown) 0.6V VCC UVLO COMPARATOR IDISCHG 6.5uA "FAST" VDAC VBIAS REGULATOR IVOSNS- 1.3mA - 12.5K ON ISOURCE 100k ENABLE COMPARATOR OC DELAY COMPARATOR S SOFTSTART CLAMP VSETPT 0.215V ERROR AMP OFF 9.1V 1.24V ON VDAC BUFFER AMP 12.5K ENABLE 1.1V BOOT SS/DEL REGDRV REGFB REGSET EAOUT FB SS/DEL DISCHARGE OVER CURRENT VCC IROSC IROSC VBIAS IROSC 250ns BLANKING + - + - + - 1.25V IIN OCSET ENABLE + - LGND SS/DEL ROSC VCC VRRDY RMPOUT VDRP VBIAS IROSC UVLO + - + - STARTUP 1.1V SET VID = 1.1V BOOT R IIN PRECONDITION LATCH S 0.6V NO CPU 0.35V SET VR11 DAC + - 3.5V 7.5V 0.62V DISABLE 1.1V Figure 7 – IR3084A Block Diagram VID Control An 8 íbit VID voltage compatible with VR 10 (see Table 1) and VR11 (see Table 2) is available at the VDAC pin. The VIDSEL pin configures the DAC for VR10 if grounded or connected to VCC (12V) and for VR11 if floated or connected to VBIAS (6.9V). The VIDSEL pin is internally pulled íup to 1.25V through a 12.5Kohm resistor. The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 0.6V threshold, monitor the VID pins and control the 8 bit Digital ítoíAnalog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amp is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the Error Amp to provide a 0.5% system accuracy. The actual VDAC voltage does not represent the system set point and has a wider tolerance. |
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