P83C524IFA datasheet(42/76 Pages) PHILIPS

42 / 76 page

1997 Dec 15

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers

P83C524; P80C528; P83C528

15.2

Idle Mode

The instruction that sets PCON.0 is the last instruction

executed in the normal operating mode before Idle mode

is activated. Once in the Idle mode, the CPU status is

preserved in its entirety: the Stack Pointer, Program

Counter, Program Status Word, Accumulator, RAM and all

other registers maintain their data during Idle mode. The

status of external pins during Idle mode is shown in

Table 28.

There are three ways to terminate the Idle mode:

• Activation of any enabled interrupt will cause PCON.0 to

be cleared by hardware terminating Idle mode. The

interrupt is serviced, and following return from interrupt

instruction RETI, the next instruction to be executed will

be the one which follows the instruction that wrote a

logic 1 to PCON.0.

• The flag bits GF0 and GF1 may be used to determine

whether the interrupt was received during normal

execution or during the Idle mode. For example, the

instruction that writes to PCON.0 can also set or clear

one or both flag bits. When Idle mode is terminated by

an interrupt, the service routine can examine the status

of the flag bits.

• The second way of terminating the Idle mode is with an

external hardware reset. Since the oscillator is still

running, the hardware reset is required to be active for

two machine cycles (24 oscillator periods) to complete

the reset operation.

• The third way of terminating the Idle mode is by internal

watchdog reset.

15.3

Power-down Mode

The instruction that sets PCON.1 is the last executed prior

to going into the Power-down mode. The oscillator is

stopped. Note that the Power-down mode also can be

entered when the watchdog has been enabled. The

Power-down mode can be terminated by an external

RESET in the same way as in the 80C51 or in addition by

any one of the two external interrupts, IE0 or IE1 (see

Section 15.4). A reset generated by the WDT terminates

the Power-down mode in the same way as an external

RESET.

The status of the external pins during Power-down mode

is shown in Table 28. If the Power-down mode is activated

while in external program memory, the port data that is

held in the P2 SFR is restored to Port 2. If the data is a

logic 1, the port pin is held HIGH during the Power-down

mode by the strong pull-up transistor p1 (see Fig.13).

Table 28 Status of the external pins during Idle and Power-down modes

MODE

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

internal

port data

Idle

external

ﬂoating

port data

address

port data

Power-down

internal

port data

Power-down

external

ﬂoating

port data

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