P83C524IFA datasheet(12/76 Pages) PHILIPS

12 / 76 page

1997 Dec 15

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers

P83C524; P80C528; P83C528

Note

1. To avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD +0.5 V or

lower than VSS −0.5 V respectively.

XTAL1

Crystal input 1: input to the inverting ampliﬁer that forms the

oscillator, and input to the internal clock generator. Receives the

external oscillator clock signal when an external oscillator is used

(see Figures 22 and 23).

VSS

Ground: circuit ground potential.

P2.0-P2.7

−28

−31

(23 n.c.)

−25

(17 n.c.)

Port 2: 8-bit quasi-bidirectional I/O Port with internal pull-ups.

During access to external memories (RAM/ROM) that use 16-bit

addresses (MOVX @DPTR) Port 2 emits the high-order address

byte (A8 to A15). Port 2 can sink/source one TTL (= 4 LSTTL)

input. It can drive CMOS inputs without external pull-ups.

PSEN

Program Store Enable output: read strobe to the external

program memory via Port 0 and Port 2. It is activated twice each

machine cycle during fetches from external program memory.

When executing out of external program memory two activations of

PSEN are skipped during each access to external data memory.

PSEN is not activated (remains HIGH) during no fetches from

external program memory. PSEN can sink/source 8 LSTTL inputs.

It can drive CMOS inputs without external pull-ups.

ALE

Address Latch Enable output: latches the LOW byte of the

address during access to external memory in normal operation. It

is activated every six oscillator periods except during an external

data memory access. ALE can sink/source 8 LSTTL inputs. It can

drive CMOS inputs without an external pull-up.

(34 n.c.)

(28 n.c.)

External Access input: when during RESET, EA is held at a TTL

HIGH level, the CPU executes out of the internal program ROM,

provided the program counter is less than 32768. When EA is held

at a TTL LOW level during RESET, the CPU executes out of

external program memory via Port 0 and Port 2. EA is not allowed

to ﬂoat.

P0.0-P0.7

−39

−43

−37

Port 0: 8-bit open drain bidirectional I/O Port. It is also the

multiplexed low-order address and data bus during accesses to

external memory (AD0 to AD7). During these accesses internal

pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.

VDD

Power supply: +5 V power supply pin during normal operation,

Idle mode and Power-down mode.

SYMBOL

DESCRIPTION

SOT 129-1 SOT 187-2 SOT 307-2

P83C524IFA Datasheet(PDF) 12 Page - NXP Semiconductors

P83C524IFA Datasheet(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL