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P83C524IFA Datasheet(PDF) 43 Page - NXP Semiconductors |
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P83C524IFA Datasheet(HTML) 43 Page - NXP Semiconductors |
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43 / 76 page  1997 Dec 15 43 Philips Semiconductors Product specification 8-bit microcontrollers P83C524; P80C528; P83C528 15.4 Wake-up from Power-down Mode The Power-down mode of the P83C528 can also be terminated by any one of the two external interrupts, IE0 or IE1. A termination with an external interrupt does not affect the internal data memory and does not affect the Special Function Registers (SFRs). This gives the possibility to exit Power-down without changing the port output levels. To terminate the Power-down mode with an external interrupt, IE0 or IE1 must be switched to be level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept LOW till the oscillator has restarted and stabilized (see Fig.21). In order to prevent any interrupt priority problems during wake-up, the priority of the desired wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. The instruction following the one that put the device into the Power-down mode will be the first one which will be executed after an interrupt has been serviced. Table 29 Internal registers status after a RESET REGISTER CONTENTS ACC 00H B 00H DPH, DPL 00H IE 0000 0000B IP X000 0000B PCH, PCL 00H PCON 0XXX 0000B PSW 00H P0 to P3 FFH SBUF Indeterminate SCON 00H SP 07H TCON 00H TMOD 00H TH0, TL0 00H TH1, TL1 00H T2CON 00H TH2, TL2 00H RCAP2H, RCAP2L 00H S1BIT X000 0000B S1INT 0XXX XXXXB S1SCS XXX0 0000B T3 00H WDCON A5H Fig.21 Wake up by external interrupt input. MBC508 - 1 oscillator stopped oscillator start up min. 20 ms power down internal timing stopped C1 C1 C1 C2 IDLE MODE LCALL interrupt routine set external interrupt latch INT0 / INT1 INT1 1 cycle INT0 2 cycles interrupts are polled |
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