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P83C524IFA Datasheet(PDF) 57 Page - NXP Semiconductors |
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P83C524IFA Datasheet(HTML) 57 Page - NXP Semiconductors |
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57 / 76 page  1997 Dec 15 57 Philips Semiconductors Product specification 8-bit microcontrollers P83C524; P80C528; P83C528 21.2 AC Characteristics 24 MHz version See notes 1, 2 and 3.; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. Notes to the AC Characteristics 16 and 24 MHz versions 1. For the AC Characteristics the following conditions are valid: a) P83C52x EBx: VDD =5 V ±10%; VSS =0 V; Tamb = 0 to +70 °C; tCK min.=63ns b) P83C52x EFx: VDD =5V ±10%; VSS =0V; Tamb = −40 to +85 °C; tCK min. = 63 ns. 2. tCK min. = 1/f max. (maximum operating frequency); tCK = clock period (see section for timing symbol definitions). 3. The maximum operating frequency is limited to 16/24 MHz and the minimum to 3.5 MHz (all versions Ixx/Exx). SYMBOL PARAMETER 24 MHZ VARIABLE CLOCK UNIT MIN. MAX. MIN. MAX. External program memory tLHLL ALE pulse duration 43 − 2 tCK−40 − ns tAVLL address set-up time to ALE 17 − tCK−25 − ns tLLAX address hold time after ALE 17 − tCK−25 − ns tLLIV time from ALE to valid instruction input − 102 − 4 tCK−65 ns tLLPL time from ALE to control pulse PSEN 17 − tCK−25 − ns tPLPH control pulse duration PSEN 80 − 3 tCK−45 − ns tPLIV time from PSEN to valid instruction input − 65 − 3 tCK−60 ns tPXIX input instruction hold time after PSEN 0 − 0 − ns tPXIZ input instruction float delay after PSEN − 17 − tCK−25 ns tAVIV address to valid instruction input − 128 − 5 tCK−80 ns tPLAZ address float time to PSEN − 10 − 10 ns External data memory tLHLL ALE pulse duration 43 − 2 tCK−40 − ns tAVLL address set-up time to ALE 17 − tCK−25 − ns tLLAX address hold time after ALE 17 − tCK−25 − ns tRLRH RD pulse duration 150 − 6 tCK−100 − ns tWLWH WR pulse duration 150 − 6 tCK−100 − ns tRLDV RD to valid data input − 118 − 5 tCK−90 ns tRHDX data hold time after RD 0 − 0 − ns tRHDZ data float delay after RD − 55 − 2 tCK−28 ns tLLDZ time from ALE to valid data input − 183 − 8 tCK−150 ns tAVDV address to valid data input − 210 − 9 tCK−165 ns tLLWL time from ALE to RD or WR 75 175 3 tCK−50 3 tCK+50 ns tAVWL time from address to RD or WR 92 − 4 tCK−75 − ns tWHLH time from RD or WR HIGH to ALE HIGH 17 67 tCK−25 tCK+ 25 ns tQVWX data valid to WR transition 12 − tCK−30 − ns tQVWH data set-up time before WR 162 − 7 tCK−130 − ns tWHQX data hold time after WR 17 − tCK−25 − ns tRLAZ address float delay after RD − 0 − 0ns |
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