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P83C524IFA Datasheet(PDF) 56 Page - NXP Semiconductors |
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P83C524IFA Datasheet(HTML) 56 Page - NXP Semiconductors |
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56 / 76 page  1997 Dec 15 56 Philips Semiconductors Product specification 8-bit microcontrollers P83C524; P80C528; P83C528 21 AC CHARACTERISTICS 21.1 AC Characteristics 16 MHz version See notes 1, 2 and 3 in Section 21.2; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. SYMBOL PARAMETER 16 MHZ VARIABLE CLOCK UNIT MIN. MAX. MIN. MAX. External program memory tLHLL ALE pulse duration 85 − 2 tCK−40 − ns tAVLL address set-up time to ALE 8 − tCK−55 − ns tLLAX address hold time after ALE 28 − tCK−35 − ns tLLIV time from ALE to valid instruction input − 150 − 4 tCK−100 ns tLLPL time from ALE to control pulse PSEN 23 − tCK−40 − ns tPLPH control pulse duration PSEN 143 − 3 tCK−45 − ns tPLIV time from PSEN to valid instruction input − 83 − 3 tCK−105 ns tPXIX input instruction hold time after PSEN 0 − 0 − ns tPXIZ input instruction float delay after PSEN − 38 − tCK−25 ns tAVIV address to valid instruction input − 208 − 5 tCK−105 ns tPLAZ address float time to PSEN − 10 − 10 ns External data memory tLHLL ALE pulse duration 85 − 2 tCK−40 − ns tAVLL address set-up time to ALE 8 − tCK−55 − ns tLLAX address hold time after ALE 28 − tCK−35 − ns tRLRH RD pulse duration 275 − 6 tCK−100 − ns tWLWH WR pulse duration 275 − 6 tCK−100 − ns tRLDV RD to valid data input − 148 − 5 tCK−165 ns tRHDX data hold time after RD 0 − 0 − ns tRHDZ data float delay after RD − 55 − 2 tCK−70 ns tLLDZ time from ALE to valid data input − 350 − 8 tCK−150 ns tAVDV address to valid data input − 398 − 9 tCK−165 ns tLLWL time from ALE to RD or WR 138 238 3 tCK−50 3 tCK+50 ns tAVWL time from address to RD or WR 120 − 4 tCK−130 − ns tWHLH time from RD or WR HIGH to ALE HIGH 23 103 tCK−40 tCK+ 40 ns tQVWX data valid to WR transition 3 − tCK−60 − ns tQVWH data set-up time before WR 288 − 7 tCK−150 − ns tWHQX data hold time after WR 13 − tCK−50 − ns tRLAZ address float delay after RD − 0 − 0ns |
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