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65053 Datasheet(PDF) 3 Page - Texas Instruments |
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65053 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 29 page ![]() www.ti.com ELECTRICAL CHARACTERISTICS TPS65053 SLVS754 – MARCH 2007 RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT Cin1-2 Input capacitor at VINLDO1, VINLDO2/3 (1) 2.2 µF COUT1 Output capacitor at VLDO1 (1) 4.7 µF COUT2-3 Output capacitor at VLDO2-3 (1) 2.2 µF ILDO1 Output current at VLDO1 400 mA ILDO2,3 Output current at VLDO2,3 200 mA TA Operating ambient temperature range –40 85 °C TJ Operating junction temperature range –40 125 °C RCC Resistor from battery voltage to VCC used for filtering(2) 1 10 Ω (2) Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly. V cc = VINDCDC1/2 = 3.6V, EN = Vcc, MODE = GND, L = 2.2µH, COUT = 22µF, TA = –40°C to 85°C typical values are at T A = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Vcc Input voltage range 2.5 6.0 V One converter, IOUT = 0 mA.PFM mode enabled (Mode = GND) device not switching, 20 30 µA EN_DCDC1 = Vin OR EN_DCDC2 = Vin; EN_LDO1= EN_LDO2 = EN_LDO3 = GND Two converters, IOUT = 0 mA, PFM mode enabled (Mode = Operating quiescent current 0) device not switching, IQ Total current into VCC, VINDCDC1/2, 32 40 µA EN_DCDC1 = Vin AND EN_DCDC2 = Vin; VINLDO1, VINLDO2/3 EN_LDO1 = EN_LDO2 = EN_LDO3 = GND One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND) device not switching, 145 210 µA EN_DCDC1 = Vin OR EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = Vin One converter, IOUT = 0 mA, Switching with no load (Mode = Vin), PWM operation 0.85 mA EN_DCDC1 = Vin OR EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND IQ Operating quiescent current into VCC Two converters, IOUT = 0 mA, Switching with no load (Mode = Vin), PWM operation 1.25 mA EN_DCDC1 = Vin AND EN_DCDC2 = Vin; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND EN_DCDC1 = EN_DCDC2 = GND I(SD) Shutdown current 9 12 µA EN_LDO1 = EN_LDO2 = EN_LDO3 = GND Undervoltage lockout threshold for V(UVLO) Voltage at VCC 1.8 2.0 V DCDC converters and LDOs EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, VIH High-level input voltage 1.2 VCC V EN_LDO3 MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, VIL Low-level input voltage 0 0.4 V EN_LDO3 MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, IIN Input bias current 0.01 1.0 µA EN_LDO3, MODE = GND or VIN POWER SWITCH VINDCDC1/2 = 3.6 V 280 630 P-channel MOSFET on DCDC1, rDS(on) m Ω resistance DCDC2 VINDCDC1/2 = 2.5 V 400 ILD_PMOS P-channel leakage current V(DS) = 6 V 1 µA VINDCDC1/2 = 3.6 V 220 450 N-channel MOSFET on DCDC1, rDS(on) m Ω resistance DCDC2 VINDCDC1/2 = 2.5 V 320 ILK_NMOS N-channel leakage current V(DS) = 6.0 V 7 10 µA Forward Current Limit DCDC1 1.19 1.4 1.65 I(LIMF) PMOS (High-Side) and 2.5 V ≤ V IN ≤ 6.0 V A DCDC2 0.85 1.0 1.15 NMOS (Low side) 3 Submit Documentation Feedback |
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