IR3080

PbF

The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay

comparator’s offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the

series resistor should be 10KΩ or less to avoid interference with the soft start function.

If SS/DEL pin is pulled below 0.9V, the converter can be disabled.

VIDPGD

(VOUT CHANGES DUE TO

LOAD AND VID CHANGES)

OCP

DELAY

OCP THRESHOLD

1.3V

VCC

NORMAL OPERATION

START-UP

POWER-DOWN

RE-START

AFTER OCP

HICCUP OVER-CURRENT

PROTECTION

1.1V

VIDPWR

8.9V

UVLO

(12V)

(3.3V)

VCCVID

(1.2V)

VIDDEL

3.91V

3.91V

SS/DEL

PWRGD

VOUT

IOUT

(VCCVID GATES

FAULT MODE)

(VCC GATES

FAULT MODE)

Figure 11. Operating Waveforms

Under Voltage Lockout (UVLO)

The UVLO function monitors the IR3080’s VCC supply pin and ensures that IR3080 has a high enough voltage to

power the internal circuit. The IR3080’s UVLO is set higher than the minimum operating voltage of compatible

Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC

exceeds 9.1V and there is no other fault. If the VCC voltage drops below 8.9V the fault latch will be set. For

converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent any

operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides

a simple 5V UVLO function. UVLO of the VIDPWR input is provided by the VID Power Good function. Adequate

voltage must be present at VIDPWR pin to allow VCCVID to reach 1.1V.

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage,

which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current

protection is triggered.

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