IR3080PBF datasheet(36/41 Pages) IRF

36 / 41 page

IR3080

PbF

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

•

Connect the ground tab under the control IC to LGND plane through a via.

•

Place the following critical components on the same layer as control IC and position them as close as possible

to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, CSS/DEL and RSS/DEL. Avoid using any via for the

connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible to

EAOUT, FB and VDRP pins. Avoid using any via for the connection.

•

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over

the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

•

Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast

transition nodes.

Page 36

IR3080PBF Datasheet(PDF) 36 Page - International Rectifier