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PCD8544 Datasheet(PDF) 5 Page - NXP Semiconductors

Part # PCD8544
Description  48 x 84 pixels matrix LCD controller/driver
PDF  32 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCD8544 Datasheet(HTML) 5 Page - NXP Semiconductors

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1999 Apr 12
5
Philips Semiconductors
Product specification
48
× 84 pixels matrix LCD controller/driver
PCD8544
6
PINNING
Note
1. For further details, see Fig.18 and Table 7.
6.1
Pin functions
6.1.1
R0 TO R47 ROW DRIVER OUTPUTS
These pads output the row signals.
6.1.2
C0 TO C83 COLUMN DRIVER OUTPUTS
These pads output the column signals.
6.1.3
VSS1,VSS2: NEGATIVE POWER SUPPLY RAILS
Supply rails VSS1 and VSS2 must be connected together.
6.1.4
VDD1,VDD2: POSITIVE POWER SUPPLY RAILS
Supply rails VDD1 and VDD2 must be connected together.
SYMBOL
DESCRIPTION
R0 to R47
LCD row driver outputs
C0 to C83
LCD column driver outputs
VSS1,VSS2
ground
VDD1,VDD2
supply voltage
VLCD1,VLCD2
LCD supply voltage
T1
test 1 input
T2
test 2 output
T3
test 3 input/output
T4
test 4 input
SDIN
serial data input
SCLK
serial clock input
D/C
data/command
SCE
chip enable
OSC
oscillator
RES
external reset input
dummy1, 2, 3, 4 not connected
6.1.5
VLCD1,VLCD2: LCD POWER SUPPLY
Positive power supply for the liquid crystal display. Supply
rails VLCD1 and VLCD2 must be connected together.
6.1.6
T1, T2, T3 AND T4: TEST PADS
T1, T3 and T4 must be connected to VSS, T2 is to be left
open. Not accessible to user.
6.1.7
SDIN: SERIAL DATA LINE
Input for the data line.
6.1.8
SCLK: SERIAL CLOCK LINE
Input for the clock signal: 0.0 to 4.0 Mbits/s.
6.1.9
D/C: MODE SELECT
Input to select either command/address or data input.
6.1.10
SCE: CHIP ENABLE
The enable pin allows data to be clocked in. The signal is
active LOW.
6.1.11
OSC: OSCILLATOR
When the on-chip oscillator is used, this input must be
connected to VDD. An external clock signal, if used, is
connected to this input. If the oscillator and external clock
are both inhibited by connecting the OSC pin to VSS, the
display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into
Power-down mode before stopping the clock.
6.1.12
RES: RESET
This signal will reset the device and must be applied to
properly initialize the chip. The signal is active LOW.



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