PCD8544 datasheet(15/32 Pages) PHILIPS

15 / 32 page

1999 Apr 12

Philips Semiconductors

Product speciﬁcation

× 84 pixels matrix LCD controller/driver

PCD8544

8.1

Initialization

Immediately following power-on, the contents of all internal

registers and of the RAM are undefined. A RES pulse

must be applied. Attention should be paid to the

possibility that the device may be damaged if not properly

reset.

All internal registers are reset by applying an external RES

pulse (active LOW) at pad 31, within the specified time.

However, the RAM contents are still undefined. The state

after reset is described in Section 8.2.

The RES input must be

≤0.3VDD when VDD reaches VDDmin

(or higher) within a maximum time of 100 ms after VDD

goes HIGH (see Fig.16).

8.2

Reset function

After reset, the LCD driver has the following state:

• Power-down mode (bit PD = 1)

• Horizontal addressing (bit V = 0) normal instruction set

(bit H = 0)

• Display blank (bit E = D = 0)

• Address counter X

6 to X0 = 0; Y2 to Y0 =0

• Temperature control mode (TC1 TC0 =0)

• Bias system (BS2 to BS0 =0)

• VLCD is equal to 0, the HV generator is switched off

(VOP6 to VOP0 =0)

• After power-on, the RAM contents are undefined.

8.3

Function set

8.3.1

BIT PD

• All LCD outputs at VSS (display off)

• Bias generator and VLCD generator off, VLCD can be

disconnected

• Oscillator off (external clock possible)

• Serial bus, command, etc. function

• Before entering Power-down mode, the RAM needs to

be filled with ‘0’s to ensure the specified current

consumption.

8.3.2

BIT V

When V = 0, the horizontal addressing is selected.

The data is written into the DDRAM as shown in Fig.6.

When V = 1, the vertical addressing is selected. The data

is written into the DDRAM, as shown in Fig.5.

8.3.3

BIT H

When H = 0 the commands ‘display control’, ‘set

Y address’ and ‘set X address’ can be performed; when

H = 1, the others can be executed. The ‘write data’ and

‘function set’ commands can be executed in both cases.

8.4

Display control

8.4.1

BITS D AND E

Bits D and E select the display mode (see Table 2).

8.5

Set Y address of RAM

Yn defines the Y vector addressing of the display RAM.

Table 3

Y vector addressing

8.6

Set X address of RAM

The X address points to the columns. The range of X is

0 to 83 (53H).

8.7

Temperature control

The temperature coefficient of VLCD is selected by bits

TC1 and TC0.

8.8

Bias value

The bias voltage levels are set in the ratio of

R-R-nR-R-R, giving a 1/(n + 4) bias system. Different

multiplex rates require different factors n (see Table 4).

This is programmed by BS2 to BS0. For Mux 1 : 48, the

optimum bias value n, resulting in 1/8 bias, is given by:

(1)

BANK

000

001

010

011

100

101

n48

–

3.928

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