PCD8544 datasheet(9/32 Pages) PHILIPS

9 / 32 page

1999 Apr 12

Philips Semiconductors

Product speciﬁcation

× 84 pixels matrix LCD controller/driver

PCD8544

7.7

Addressing

Data is downloaded in bytes into the 48 by 84 bits RAM

data display matrix of PCD8544, as indicated in

Figs. 3, 4, 5 and 6. The columns are addressed by the

address pointer. The address ranges are: X 0 to 83

(1010011), Y 0 to 5 (101). Addresses outside these

ranges are not allowed. In the vertical addressing mode

(V = 1), the Y address increments after each byte (see

Fig.5). After the last Y address (Y = 5), Y wraps around

to 0 and X increments to address the next column. In the

horizontal addressing mode (V = 0), the X address

increments after each byte (see Fig.6). After the last

X address (X = 83), X wraps around to 0 and

Y increments to address the next row. After the very last

address (X = 83 and Y = 5), the address pointers wrap

around to address (X=0andY=0).

7.7.1

DATA STRUCTURE

Fig.4 RAM format, addressing.

handbook, full pagewidth

MGL638

LSB

MSB

Y-address

X-address

Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

handbook, halfpage

MGL639

503

Y-address

X-address

PCD8544 Datasheet(PDF) 9 Page - NXP Semiconductors