MS1100

Hangzhou Ruimeng Technology Co.,Ltd

VERSION : V1.10

2023.05.22

http://www.relmon.com

- PAGE 8 -

SCL

SDA

P

S

P

S

t(BUF)

t(HDSTA)

t(LOW)

tR

t(HIGH)

tF

t(HDDAT)

t(SUDAT)

t(SUSTA)

t(HDSTA)

t(SUSTO)

Figure 1. I2C Timing Diagram

Table 3. Timing Diagram Definitions

Parameter

Fast-Speed Mode

Unit

Min

Max

t(SCLK)

SCLK Operating Frequency

0.4

MHz

t(BUF)

Bus START to STOP Idle Time

600

ns

t(HDSTA)

START Hold Time

600

ns

t(SUSTA)

Repeated START Setup Time

600

ns

t(SUSTO)

STOP Setup Time

600

ns

t(HDDAT)

Data Hold Time

0

ns

t(SUDAT)

Data Setup Time

100

ns

t(LOW)

SCLK Clock Low Level Period

1300

ns

t(HIGH)

SCLK Clock High Level Period

600

ns

tF

Clock/Data Fall Time

300

ns

tR

Clock/Data Rise Time

300

ns

Result Register

The 16-bit result register contains the conversion result in binary two’s complement format. After reset or

power-up, the result register is cleared 0, and remains until the first conversion is completed. The format of

result register is shown in Table 4.

Table 4. Result Register

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Configuration Register

The 8-bit configuration register can be used to control the operation mode, update rate and PGA. The

format of configuration register is shown in Table 5. The default setting is 8CH.

Table 5. Configuration Register

Bit

7

6

5

4

3

2

1

0

Name

ST/DRDY

0

0

SC

DR1

DR0

PGA1

PGA0

Default

1

0

0

0

1

1

0

0