REV. 0

–14–

AD9948

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9948 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for gener-

ating the timing used for both the CCD and the AFE; the reset

gate RG, horizontal drivers H1–H4, and the SHP/SHD sample

clocks. A unique architecture makes it routine for the system

designer to optimize image quality by providing precise control

over the horizontal CCD readout and the AFE correlated

double sampling.

Timing Resolution

The Precision Timing core uses a 1

× master clock input (CLI)

as a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 4 illustrates how the internal timing core

divides the master clock period into 48 steps or edge positions.

Therefore, the edge resolution of the Precision Timing core is

the Applications Information section.

High Speed Clock Programmability

Figure 5 shows how the high speed clocks, RG, H1–H4, SHP,

and SHD, are generated. The RG pulse has programmable rising

and falling edges, and may be inverted using the polarity control.

The horizontal clocks H1 and H3 have programmable rising and

falling edges, and polarity control. The H2 and H4 clocks are

always inverses of H1 and H3, respectively. Table X summarizes

the high speed timing registers and their parameters.

Each edge location setting is 6 bits wide, but only 48 valid edge

locations are available. Therefore, the register values are mapped

into four quadrants, with each quadrant containing 12 edge

locations. Table XI shows the correct register values for the

corresponding edge locations.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

P[0]

P[48] = P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

...

...

CLI

POSITION

Figure 4. High Speed Clock Resolution From CLI Master Clock Input

H1/H3

H2/H4

CCD SIGNAL

RG

(1)

(2)

(3)

(4)

(5)

(6)

PROGRAMMABLE CLOCK POSITIONS:

1. RG RISING EDGE

2. RG FALLING EDGE

3. SHP SAMPLE LOCATION

4. SHD SAMPLE LOCATION

5. H1/H3 RISING EDGE POSITION

6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)

Figure 5. High Speed Clock Programmable Locations

Table X. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters

Parameter

Length

Range

Description

Polarity

1b

High/Low

Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion).

Positive Edge

6b

0–47 Edge Location

Positive Edge Location for H1/H3 and RG.

Negative Edge

6b

0–47 Edge Location

Negative Edge Location for H1/H3 and RG.

Sample Location

6b

0–47 Sample Location

Sampling Location for SHP and SHD.

Drive Control

3b

0–7 Current Steps

Drive Current for H1–H4 and RG Outputs, 0–7 Steps of 4.1 mA Each.

DOUT Phase

6b

0–47 Edge Location

Phase Location of Data Outputs with Respect to Pixel Period.