AD9948 datasheet(20/28 Pages) AD

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REV. 0

–20–

AD9948

6dB ~ 42dB

CCDIN

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

10-BIT

ADC

VGA

DAC

CLAMP LEVEL

VGA GAIN

CDS

INTERNAL

VREF

2V FULL SCALE

0dB ~ 18dB

PRECISION

TIMING

GENERATION

SHP

SHD

PxGA

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT

PHASE

V-H

TIMING

GENERATION

SHP SHD

DOUT

PHASE

CLPOB

PBLK

1.0V

2.0V

DOUT

AD9948

PxGA GAIN

REGISTERS

0dB, –2dB, –4dB

1.0 F 1.0 F

1.0 F

Figure 15. Analog Front End Functional Block Diagram

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9948 signal processing chain is shown in Figure 15. Each

processing step is essential in achieving a high quality image from

the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal,

adc restore circuit is used with an external 0.1

µF series cou-

pling capacitor. This restores the dc level of the CCD signal to

approximately 1.5 V to be compatible with the 3 V supply voltage

of the AD9948.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

shown in Figure 5 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and the CCD signal level, respectively. The placement of

the SHP and SHD sampling edges is determined by the setting

of the SAMPCONTROL register located at Address 0x63.

Placement of these two clock signals is critical in achieving the

best performance from the CCD.

The gain in the CDS is fixed at 0 dB by default. Using Bits D10

and D11 in the AFE operation register, the gain may be reduced

to –2 dB or –4 dB. This will allow the AD9948 to accept an input

signal of greater than 1 V p-p. See Table VIII for register details.

Table XVI. Adjustable CDS Gain

Operation Register Bits

D11

D10

CDS Gain

Max CDS Input

0 dB

1.0 V p-p

–2 dB

1.2 V p-p

–4 dB

1.6 V p-p

0 dB

1.0 V p-p

PxGA

The PxGA provides separate gain adjustment for the individual

color pixels. A programmable gain amplifier with four separate

values, the PxGA has the capability to multiplex its gain value on

a pixel-to-pixel basis (see Figure 16). This allows lower output

color pixels to be gained up to match higher output color pixels.

Also, the PxGA may be used to adjust the colors for white bal-

ance, reducing the amount of digital processing that is needed.

The four different gain values are switched according to the color

steering circuitry. Three different color steering modes for differ-

ent types of CCD color filter arrays are programmable in the AFE

CTLMODE register at Address 0x03 (see Figures 18a to 18c for

timing examples). For example, progressive steering mode accom-

modates the popular Bayer arrangement of red, green, and blue

filters (see Figure 17a).

COLOR

STEERING

CONTROL

4:1

MUX

GAIN0

GAIN1

GAIN2

GAIN3

PxGA

PxGA STEERING

MODE

SELECTION

PxGA GAIN

REGISTERS

CONTROL

BITS D0–D1

SHP/SHD

VGA

CDS

Figure 16. PxGA Block Diagram

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