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AD9948 Datasheet(PDF) 25 Page - Analog Devices

Part # AD9948
Description  10-Bit CCD Signal Processor with Precision Timing??Core
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9948 Datasheet(HTML) 25 Page - Analog Devices

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REV. 0
AD9948
–25–
Driving the CLI Input
The AD9948’s master clock input (CLI) may be used in two
different configurations, depending on the application. Figure 23a
shows a typical dc-coupled input from the master clock source.
When the dc-coupled technique is used, the master clock signal
should be at standard 3 V CMOS logic levels. As shown in
Figure 23b, a 1000 pF ac coupling capacitor may be used
between the clock source and the CLI input. In this configura-
tion, the CLI input will self-bias to the proper dc voltage level
of approximately 1.4 V. When the ac-coupled technique is
used, the master clock signal can be as low as
±500 mV in
amplitude.
18
CCD IMAGER
SIGNAL
OUT
19
14
15
21
27
H2
RG
H3
H4
H1
H2
H1
RG
AD9948
CCDIN
Figure 22a. CCD Connections (2 H-Clock)
CCD IMAGER
SIGNAL
OUT
14
15
21
27
RG
H3
H4
H2
H1
RG
AD9948
CCDIN
H2
H1
18
19
H1
H2
Figure 22b. CCD Connections (4 H-Clock)
CLI
25
MASTER CLOCK
AD9948
ASIC
Figure 23a. CLI Connection, DC-Coupled
CLI
25
MASTER CLOCK
AD9948
ASIC
LPF
1nF
Figure 23b. CLI Connection, AC-Coupled



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