REV. 0

AD9948

–15–

Table XI. Precision Timing Edge Locations

Quadrant

Edge Location (Decimal)

Register Value (Decimal)

Register Value (Binary)

I0 to 11

0 to 11

000000 to 001011

II

12 to 23

16 to 27

010000 to 011011

III

24 to 35

32 to 43

100000 to 101011

IV

36 to 47

48 to 59

110000 to 111011

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9948

features on-chip output drivers for the RG and H1–H4 outputs.

These drivers are powerful enough to directly drive the CCD

inputs. The H-driver and RG driver current can be adjusted

for optimum rise/fall time into a particular load by using the

DRVCONTROL register (Address x062). The DRVCONTROL

register is divided into five different 3-bit values, each one being

adjustable in 4.1 mA increments. The minimum setting of 0 is

equal to OFF or three-state, and the maximum setting of 7 is

equal to 30.1 mA.

As shown in Figure 6, the H2/H4 outputs are inverses of H1/H3.

The internal propagation delay resulting from the signal inversion

is less than l ns, which is significantly less than the typical rise

time driving the CCD load. This results in a H1/H2 crossover

voltage at approximately 50% of the output swing. The crossover

voltage is not programmable.

Digital Data Outputs

The AD9948 data output phase is programmable using the

DOUTPHASE register (Address x064). Any edge from 0 to 47

may be programmed, as shown in Figure 7a. The pipeline delay

for the digital data output is shown in Figure 7b.

FIXED CROSSOVER VOLTAGE

H1/H3

H2/H4

H2/H4

H1/H3

<<

Figure 6. H-Clock Inverse Phase Relationship

NOTES

1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.

P[0]

P[48] = P[0]

CLI

1 PIXEL PERIOD

P[12]

P[24]

P[36]

DOUT

Figure 7a. Digital Output Phase Adjustment

NOTES

DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0.

HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

DOUT

CCDIN

CLI

SHD

(INTERNAL)

N

N+1

N+2

N+12

N+11

N+10

N+9

N+8

N+7

N+6

N+5

N+4

N+3

N+13

N–13

N–3

N–4

N–5

N–6

N–7

N–8

N–9

N–10

N–11

N–12

N–2

N–1

N+1

N

SAMPLE PIXEL N

PIPELINE LATENCY = 11 CYCLES

N–1

Figure 7b. Pipeline Delay for Digital Data Output