Electronic Components Datasheet Search
  English  ▼

X  

TCM8000FN Datasheet(PDF) 6 Page - Texas Instruments

Part # TCM8000FN
Description  CELLULAR TELEPHONE AUDIO PROCESSOR
PDF  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TCM8000FN Datasheet(HTML) 6 Page - Texas Instruments

Back Button TCM8000FN Datasheet HTML 2Page - Texas Instruments TCM8000FN Datasheet HTML 3Page - Texas Instruments TCM8000FN Datasheet HTML 4Page - Texas Instruments TCM8000FN Datasheet HTML 5Page - Texas Instruments TCM8000FN Datasheet HTML 6Page - Texas Instruments TCM8000FN Datasheet HTML 7Page - Texas Instruments TCM8000FN Datasheet HTML 8Page - Texas Instruments TCM8000FN Datasheet HTML 9Page - Texas Instruments TCM8000FN Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 19 page
background image
TCM8000
CELLULAR TELEPHONE AUDIO PROCESSOR
SCTS041A – D4086, AUGUST 1992 – REVISED APRIL 1993
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
detailed description – miscellaneous
crystal oscillator
A low-power crystal oscillator is provided to generate the master clock signal for the switched-capacitor filters.
Sampling frequencies and internal divide ratios have been selected to allow a low cost 3.58-MHz crystal to be
used. No external components except the crystal are required.
DAC
A four-bit digital-to-analog (DAC) converter provides sixteen levels from GND to VBRX in linear steps. The DAC
can be used to set limit levels by controlling TXLIM or RXLIM. Its output is unbuffered and should only be used
to drive high-impedance loads.
standby mode
The standby mode disables all signal paths with the exception of the receive data path. In the standby mode,
current consumption is reduced to less than 4 mA.
digital interface
The TCM8000 is configured using a three-wire digital interface. Eight-bit words, comprised of four address and
four data bits, are applied in serial to DATA and clocked into the device on the rising edge of DCLK. The data
is transferred to internal registers by pulsing the LOAD signal high (see Figure 1). All internal registers are reset
low on power up.
DCLK
DATA
LOAD
AD3
AD2
AD1
AD0
D3
D2
D1
D0
Figure 1. Serial Interface Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com