 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TAS5414 Datasheet(PDF) 22 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TAS5414 Datasheet(HTML) 22 Page - Texas Instruments |
|
|
22 / 44 page  www.ti.com Random Read A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I CDevice Addressand 2 Read/WriteBit Subaddress DataByte D7 D6 D1 D0 ACK I CDevice Addressand Read/WriteBit 2 Not Acknowledge R/W A1 A1 RepeatStart Condition T0036-03 Sequential Read A6 A0 ACK Acknowledge I CDevice Addressand Read/WriteBit 2 R/W A6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge LastDataByte ACK FirstDataByte RepeatStart Condition Not Acknowledge I CDevice Addressand Read/WriteBit 2 Subaddress OtherDataBytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 T0036-04 TAS5414 TAS5424 SLOS514 – FEBRUARY 2007 As shown in Figure 19, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the TAS5414 or TAS5424 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5414 or TAS5424 address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5414 or TAS5424 again responds with an acknowledge bit. Next, the TAS5414 or TAS5424 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer. Figure 19. Random Read Transfer A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS5414 or TAS5424 to the master device as shown in Figure 20. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C subaddress by one. Note: The fault registers do not have sequential read capabilities. Figure 20. Sequential Read Transfer 22 Submit Documentation Feedback |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
