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TMD2636 Datasheet(PDF) 30 Page - OSRAM GmbH |
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TMD2636 Datasheet(HTML) 30 Page - OSRAM GmbH |
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30 / 48 page ![]() Datasheet, Public Page 29 [v2-00] 2023-Jan-04 Document Feedback TMD2636 − Register Description CALIBSTAT Register (0xDC) Figure 41: CALIBSTAT Register INTENAB Register (0xDD) Figure 42: INTENAB Register The PIM (Proximity Interrupt Mode) bit selects the condition under which the PINT status bit and the corresponding interrupt (if enabled with PIEN) will be asserted. Addr: 0xDC CALIBSTAT Bit Bit Name Default Access Bit Description 7:3 Reserved 00000 RW Reserved. Must be set to default value. 2 OFFSET_ ADJUSTED 0RW Bit is set when the proximity offset has been automatically decremented if AUTO_OFFSET_ADJ = 1 (see CALIBCFG register). This bit can be cleared by writing 1 to it or setting AUTO_ OFFSET_ADJ to 0. 1 Reserved 0 RW Reserved. Must be set to default value. 0 CALIB_FINISHED 0 RW This flag indicates that calibration has finished. This bit is a copy of the CINT bit in the STATUS register. It will be cleared when the CINT bit is cleared. Addr: 0xDD INTENAB Bit Bit Name Default Access Bit Description 7:6 Reserved 00 RW Reserved. Must be set to default value. 5PIM 0 RW Proximity Interrupt Mode 0 = Level based 1 = State based 4 PIEN 0 RW Proximity Interrupt Enable 3 PSIEN 0 RW Proximity Saturation Interrupt Enable 2 CIEN 0 RW Calibration Interrupt Enable 1 ZIEN 0 RW Zero Detect Interrupt Enable 0 Reserved 0 RW Reserved. Must be set to default value. |
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