56F8322 datasheet(106/136 Pages) FREESCALE

106 / 136 page

56F8322 Techncial Data, Rev. 16

106

Freescale Semiconductor

Preliminary

Table 10-6 Power-On Reset Low Voltage Parameters

Characteristic

Symbol

Min

Typ

Max

Units

POR Trip Point Rising1

1. Both VEI2.5 and VEI3.3 thresholds must be met for POR to be released on power-up.

PORR

———

POR Trip Point Falling

PORF

1.75

1.8

1.9

LVI, 2.5V Supply, trip point2

2. When VDD_CORE drops below VEI2.5, an interrupt is generated.

VEI2.5

—2.14—

LVI, 3.3V supply, trip point3

3. When VDD_CORE drops below VEI3.3, an interrupt is generated.

VEI3.3

—2.7

—

Bias Current

I bias

—110

130

μA

Table 10-7 Current Consumption per Power Supply Pin (Typical)

On-Chip Regulator Enabled (OCR_DIS = Low)

Mode

IDD_IO

1. No Output Switching (Output switching current can be estimated from I = CVf for each output)

2. Includes Processor Core current supplied by internal voltage regulator

IDD_ADC

IDD_OSC_PLL

Test Conditions

RUN1_MAC

115mA

25mA

2.5mA

• 60MHz Device Clock

• All peripheral clocks are enabled

• Continuous MAC instructions with fetches from

Data RAM

• ADC powered on and clocked

Wait3

60mA

μA2.5mA

• 60MHz Device Clock

• All peripheral clocks are enabled

• ADC powered off

Stop1

5.7mA

μA360μA

• 4MHz Device Clock

• All peripheral clocks are off

• Relaxation oscillator is on

• ADC powered off

• PLL powered off

Stop2

5mA

μA145μA

• Relaxation oscillator is off

• All peripheral clocks are off

• ADC powered off

• PLL powered off

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