Analog Integrated Circuit Device Data

Freescale Semiconductor

33

33874

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

Introduction

This thermal addendum is provided as a supplement to the 33874 technical

datasheet. The addendum provides thermal performance information that may be

critical in the design and development of system applications. All electrical,

application, and packaging information is provided in the datasheet.

Packaging and Thermal Considerations

This package is a dual die package. There are two heat sources in the package

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not

meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained

by measurement and simulation according to the standards listed below.

Figure 10. Testboard According to JEDEC

HIGH-SIDE SWITCH

33874

PNA SUFFIX

98ARL10596D

24-PIN PQFN (12 x 12)

Note For package dimensions, refer to

the 33874 data sheet.

=

.

Table 18. Thermal Performance Comparison

Thermal

Resistance

1 = Power Chip, 2 = Logic Chip [

°C/W]

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

(1), (2)

20

16

39

(2), (3)

62.0

26

(1), (4)

53

40

73

(5)

<0.5

0.0

1.0

Notes:

1.

Per JEDEC JESD51-2 at natural convection, still air

condition.

2.

2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

3.

Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

4.

Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5.

Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

1.0

1.0

0.2

0.2