33874 datasheet(17/37 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33874

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

SPI PROTOCOL DESCRIPTION

The SPI interface has a full duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),

and Chip Select (CS).

The SI/SO pins of the 33874 follow a first-in first-out (D15

to D0) protocol, with both input and output words transferring

the most significant bit (MSB) first. All inputs are compatible

with 5.0 V CMOS logic levels.

Figure 9. Single 16-Bit Word SPI Communication

OPERATIONAL MODES

The 33874 has four operating modes: Sleep, Normal,

Fault, and Fail-Safe. Table 5 summarizes details contained in

succeeding paragraphs.

SLEEP MODE

The Default mode of the 33874 is the Sleep mode. This is

the state of the device after first applying battery voltage

(VPWR) prior to any I/O transitions. This is also the state of the

device when the WAKE and RST are both logic [0]. In the

Sleep mode, the output and all unused internal circuitry, such

as the internal 5.0 V regulator, are off to minimize current

draw. In addition, all SPI-configurable features of the device

are as if set to logic [0]. The 33874 will transition to the

Normal or Fail-Safe operating modes based on the WAKE

and RST inputs as defined in Table 5.

NORMAL MODE

The 33874 is in Normal mode when:

•VPWR and VDD are within the normal voltage range.

• RST pin is logic [1].

• No fault has occurred.

FAIL-SAFE MODE

FAIL-SAFE MODE AND WATCHDOG

If the FSI input is not grounded, the watchdog timeout

detection is active when either the WAKE or RST input pin

transitions from logic [0] to logic [1]. The WAKE input is

capable of being pulled up to VPWR with a series of limiting

CSB

SCLK

D15

D14

D13

D12

D11

D10

OD12

OD13

OD14

OD15

OD6

OD7

OD8

OD9

OD10

OD11

OD1

OD2

OD3

OD4

OD5

RSTB is in a logic H state during the above operation.

DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

NOTES:

OD0

device.

1. RST is a logic [1] state during the above operation.

2. D15

:D0 relate to the most recent ordered entry of data into the device.

3. OD15

:OD0 relate to the first 16 bits of ordered fault and status data out of the device.

Notes

Table 5. Fail-Safe Operation and Transitions to Other

33874 Modes

Mode

Wake RST WDTO

Comments

Sleep

Device is in Sleep mode. All

outputs are OFF

Normal

Normal mode. Watchdog is

active if enabled.

Fault

Device is currently in fault

mode. The faulted output(s)

is (are) OFF.

Fail-

Safe

Yes

Watchdog has timed out and

the device is in Fail-Safe

Mode. The outputs are as

configured with the RFS

resistor connected to FSI.

RST

and WAKE must go

from logic [1] to logic [0]

simultaneously to bring the

device out of the Fail-safe

mode or momentarily tied the

FSI pin to ground.

x = Don’t care.

33874 Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

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