56F807 datasheet(33/60 Pages) FREESCALE

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External Bus Asynchronous Timing

56F807 Technical Data Technical Data, Rev. 15

Freescale Semiconductor

3.5 External Bus Asynchronous Timing

Table 3-10 External Bus Asynchronous Timing1,2

Operating Conditions: V

SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol

Min

Max

Unit

Address Valid to WR Asserted

tAWR

6.5

—

WR Width Asserted

Wait states = 0

Wait states > 0

tWR

7.5

(T*WS)+7.5

—

WR Asserted to D0–D15 Out Valid

tWRD

—T + 4.2

Data Out Hold Time from WR Deasserted

tDOH

4.8

—

Data Out Set Up Time to WR Deasserted

Wait states = 0

Wait states > 0

tDOS

2.2

(T*WS)+6.4

—

RD Deasserted to Address Not Valid

tRDA

0—

Address Valid to RD Deasserted

Wait states = 0

Wait states > 0

tARDD

18.7

(T*WS) + 18.7

—

Input Data Hold to RD Deasserted

tDRD

0—

RD Assertion Width

Wait states = 0

Wait states > 0

tRD

(T*WS)+19

—

Address Valid to Input Data Valid

Wait states = 0

Wait states > 0

tAD

—

(T*WS)+1

Address Valid to RD Asserted

tARDA

-4.4

—

RD Asserted to Input Data Valid

Wait states = 0

Wait states > 0

tRDD

—

2.4

(T*WS) + 2.4

WR Deasserted to RD Asserted

tWRRD

6.8

—

RD Deasserted to RD Asserted

tRDRD

0—

WR Deasserted to WR Asserted

tWRWR

14.1

—

RD Deasserted to WR Asserted

tRDWR

12.8

—

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