DLPC7530 datasheet(21/112 Pages) TI1

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available as a general purpose I/O). More information on GPIO allocations for specific product configurations can be found in Section

6.3.8.

(4)

All GPIO that are available as a general purpose I/O must be configured as an input, a standard output, or an open-drain output. This

is set in the flash configuration. Configure unused GPIO as a logic zero output and leave unconnected, otherwise an external pullup or

pulldown resistor is required to avoid a floating input. The reset default for all GPIO is as an input signal.

An external pullup resistor (≤ 10kΩ) is required for each signal configured as open-drain output.

Table 4-11. Clock and Support

TYPE(1)

DESCRIPTION

NAME

NO.

REFCLKA_I

AJ18

Crystal A Input: Reference clock crystal input(2) (3)

REFCLKA_O

AK18

O10

Crystal A Output: Reference clock crystal output(2)

REFCLKB_I

B16

I14

Crystal B Input: Reference clock crystal input(2) (3)

REFCLKB_O

A16

O15

Crystal B Output: Reference clock crystal output(2)

OCLKA

AD30

General Purpose Output Clock A (4)

Targeted for driving Color Wheel motor controller. Frequency is software programmable, with a

power-up default frequency of 0.77MHz.

Note: The output frequency is not affected by non-power-up reset operations (that is, the

system holds the last programmed value until system is power cycled).

(1)

See Table 4-13 for more information on I/O definitions.

(2)

For more information on this signal see Section 5.12.

(3)

For applications where an external oscillator is used in place of a crystal, use an oscillator to drive this pin.

(4)

For more information on this signal see Section 5.22.

Table 4-12. Power and Ground

TYPE(1)

DESCRIPTION

NAME

NO.

VDD115_PLLMA

AE18

PWR

1.15V digital power for MCG (Controller Clock Generator A)

PLL

VDD115_PLLMB

F15

PWR

1.15V digital power for MCG (Controller Clock Generator B)

PLL

VAD115_PLLS

F16

PWR

1.15V analog power for SCG doubler PLL

VAD18_PLLMA

AE19

PWR

1.8V analog power for MCG (Controller Clock Generator A)

PLL

VAD18_PLLMB

F14

PWR

1.8V analog power for MCG (Controller Clock Generator B)

PLL

VAD33_OSCA

Y18

PWR

3.3V analog power for Crystal-OSC

VAD33_OSCB

L17

PWR

3.3V analog power for Crystal-OSC

VAD115_FPD

F7,F9,F11,J6,L12

PWR

1.15V analog power for FPD

VDD33_FPD

E6,E8,E10,E12,E14,G6,L11,L13

PWR

3.3V digital power for FPD

VAD115_VX1

F24,L18

PWR

1.15V analog power for VX1

VAD18_VX1

E18,L19

PWR

1.8V analog power for VX1

VAD33_USB

D27,E26,F25

PWR

3.3V analog power for USB

VDD18_SCS

L16,R6,T25,AE16

PWR

1.8V digital power for SCS DRAM

VDD121_SCS

L15,N11,P20,U11,V20,Y16

PWR

1.21-V digital power for SCS SRAM

VAD115_HSSI

Y14,Y19,AF7,AF9,AF11,AF13AF21,A

F23,AF25

PWR

1.15V analog power for HSSI interface

VAD115_HSSI0_PLL

AE22

PWR

1.15V analog power for HSSI-0 PLL

VAD115_HSSI1_PLL

AE10

PWR

1.15V analog power for HSSI-1 PLL

VDD33_HSSI

Y12,Y20,AE8,AE12,AE20,AE24

PWR

3.3V digital power for HSSI interface

VAD18_LSIF

Y15,AE13,AE14

PWR

1.8V analog power for DMD low-speed interface

LVDS_VREFTEST

AF16

Manufacturing test use only; must be left open-unconnected

VDD115

L14,L20,M11,N20,P11,R20,T11,U20,

V11,W20,Y11,Y13,Y17

PWR

1.15V core power

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