DLPC7530 datasheet(49/112 Pages) TI1

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VSYNC_WE

HSYNC_CS

DATAEN_CMD

tp_vsw

1 Frame

tp_vbp

tp_vfp

HSYNC_CS

DATAEN_CMD

tp_hsw

1 Line

tp_hfp

tp_hbp

PDATA(23/15:0)

PCLK

n-2

n-1

(This diagram assumes the VSYNC

active edge is the rising edge)

(This diagram assumes the HSYNC

active edge is the rising edge)

Figure 5-16. Source Frame Timing

5.20 Synchronous Serial Port Interface Timing Requirements

For SSP0, SSP1, and SSP2(1)(2)

PARAMETER

MIN

MAX

UNIT

SSP Controller

fclock

Clock frequency, SSPx_CLK

50% to 50% reference points

0.38

39.0

MHz

tclock

Clock Period, SSPx_CLK

50% to 50% reference points

25.6

3632

tw(L)

Pulse duration low, SSPx_CLK

50% to 50% reference points

12.0

tw(H)

Pulse duration high, SSPx_CLK

50% to 50% reference points

12.0

tdelay

Output Delay – SSPx_TXD (MOSI)

–2.5

2.5

tsu

Setup time – SSPx_RXD (MISO)

50% to 50% reference points

15.0

hold time – SSPx_RXD (MISO)

50% to 50% reference points

Transition time (tr and tf- SSPx_RXD

20% to 80% reference points

1.5

tclkjit

Clock jitter, SSPx_CLK

300

tdelay∆

Clock output delay ∆ { | tw(H) – tw(L) | }

500

SSP Peripheral

tdelay

Output Delay – SSPx_TXD (MOSI)

tsu

Setup time – SSPx_RXD (MISO)

50% to 50% reference points

2.5

Hold time – SSPx_RXD (MISO)

50% to 50% reference points

2.5

(1)

The DLPC7530 SPI interfaces support SPI Modes 0, 1, 2, and 3 (that is, both clock polarities and both clock phases) as shown in

Table 5-2 and Figure 5-17. As such, each SPI interface configuration must be setup to match the SPI mode being used.

(2)

In most SPI applications, one clock edge is used by both controller and peripheral devices for transmitting data while the other edge

is use by both for sampling received data. This is referred to as Standard SPI Protocol. To maximize the SPI_CLK frequency potential,

SPI controllers can alternatively be designed to sample the data in (MISO) bit on the same clock edge used to transmit the next data

out (MOSI) bit. This is referred to as Enhanced SPI Protocol. The DLPC7530 SPI controller implementation supports both protocols

(part of SPI interface configuration), however, to be able to use the "Enhanced SPI Protocol," the peripheral device must meet the

requirement shown in Figure 5-18.

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