DLPC7530 datasheet(96/112 Pages) TI1

96 / 112 page

135

o < Angle < 225o

Shield

Differential Pair

Shield

Figure 9-15. USB Routing Example

Additional USB layout guidelines for TXRTUNE

• Use the shortest possible connection lengths for the resistor between TXRTUNE and ground.

• Use ground layer and ground guard traces to shield the wires and resistor.

9.1.8 DMD Interface Layout Considerations

The DLPC7530 controller HSSI differential interface waveform quality and timing is dependent on the total length

of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well

matched the lengths are across the interface. Thus, ensuring a positive timing margin requires attention to many

factors.

DLPC7530 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding

data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB

design recommendations are provided in Table 9-8, Figure 9-16, and the paragraph below as a starting point for

the customer.

Table 9-8. PCB Recommendations for DMD Interface(1)(2)

PARAMETER

MIN

MAX

UNIT

Trace Width

5.7

mils

Intra-lane Trace Spacing

5.3

mils

TSPP

Inter-lane trace spacing(3)

48.3

mils

(1)

Recommendations to achieve the desired nominal differential impedance as specified by RDIFF in Section 5.7.

(2)

These parameters show recommendations based on the micro-strip design shown in Figure 9-16. This design minimizes signal loss

to support longer trace lengths at the expense of electromagnetic interference (EMI). The designer has the option to use a stripline

design for shorter trace lengths and to target minimizing EMI at the expense of signal loss.

(3)

A reduced inter-lane spacing can be used to escape the controller ball field, however, widen this spacing to at least the stated

minimum after the escape.

Tspp

Ground Plane

Signal Traces

Differential Pair #1

Differential Pair #2

Figure 9-16. DMD Differential Layout Recommendations

Additional DMD interface layout guidelines:

• Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the

number of necessary vias to two. If two are required, place one at each end of the line (one at the controller

and one at the DMD).

• Route the differential signal pairs over a single ground or power plane using a Micro-strip line configuration.

• Do not route the differential signal pairs over the slit of power or ground planes.

• Ensure the bend angles associated with the differential signal pairs are between 135° and 225°.

• Route the single-ended signal in a way that minimizes the number of vias required. Limit the number of

necessary vias to two. If two are required, place one at each end of the line (one at the controller and one at

the DMD).

• Avoid stubs.

DLPC7530

DLPS271 – APRIL 2024

www.ti.com

Submit Document Feedback

Product Folder Links: DLPC7530

DLPC7530 Datasheet(PDF) 96 Page - Texas Instruments

DLPC7530 Datasheet(HTML) 96 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL