DLPC7530 datasheet(43/112 Pages) TI1

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tX2

1 UI

VOD(max)

VOD(min)

±VOD(min)

±VOD(max)

0 V

tEYE

tX1

tX2

tX1

Figure 5-11. HSSI Eye Characteristics

5.15 DMD Low-Speed LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

fclock

119.966

120

120.034

MHz

tR (1)

Differential output rise time

(10% to 90%)

250

tF (1)

Differential output fall time

(10% to 90%)

250

DCD

Duty cycle distortion

45%

55%

(1)

Rise and fall times are associated with VDIFF-pp, as shown in Figure 5-12 .

+VDIFF(PP)/2

(0 V) 50

100

tF .

VDIFF(PP)

±VDIFF(PP)/2

tR.

VCM is removed when signals are viewed differentially.

Figure 5-12. DMD Low-Speed Differential Timing Parameters

5.16 V-by-One Interface General Timing Requirements

PARAMETER(1)

MIN

MAX

UNIT

fclock

Source clock frequency

40 (1 lane)

20 (1 lane with pixel

repeat) (2)

600 (8

lanes)

MHz

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DLPC7530

DLPS271 – APRIL 2024

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