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DLPC7530 Datasheet(PDF) 36 Page - Texas Instruments |
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DLPC7530 Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 112 page  5.12 System Oscillator Timing Requirements PARAMETER MIN NOM MAX UNIT ƒclock Clock frequency, REFCLKA(1) (2) PLLA: 40MHz 39.9960 40.000 40.0040 MHz tc Cycle time, REFCLKA(1) PLLA: 40MHz 24.9975 25.000 25.0025 ns tw(H) Pulse duration(3), REFCLKA, high PLLA: 40MHz 50% to 50% reference points (signal) 11.25 ns tw(L) Pulse duration(3), REFCLKA, low PLLA: 40MHz 50% to 50% reference points (signal) 11.25 ns tt Transition time(3), REFCLKA, tt = tƒ / tr PLLA: 40MHz 20% to 80% reference points (signal) 2.5 ns tjp Long term periodic jitter(3), REFCLKA (that is the deviation in period from ideal period due solely to high frequency jitter) PLLA: 40MHz 18 ps fclock Clock frequency, REFCLKB(1) PLLB: 38MHz 37.9962 38.000 38.0038 MHz tc Cycle time, REFCLKB(1) PLLB: 38MHz 26.3132 26.3157 26.3184 ns tw(H) Pulse duration(3), REFCLKB, high PLLB: 38MHz 50% to 50% reference points (signal) 11.84 ns tw(L) Pulse duration(3), REFCLKB, low PLLB: 38MHz 50% to 50% reference points (signal) 11.84 ns tt Transition time(3), REFCLKB, tt = tƒ / tr PLLB: 38MHz 20% to 80% reference points (signal) 2.63 ns tjp Long term periodic jitter(3), REFCLKB (that is the deviation in period from ideal period due solely to high frequency jitter) PLLB: 38MHz 18 ps (1) The REFCLK inputs do not support spread spectrum clock spreading. (2) Multi-controller systems require that a single oscillator be used to drive the REFCLKA input for all controllers in the system. (3) Applies only when driven through an external digital oscillator. This is a 1-sigma RMS value. REFCLK 50% 80% 20% 50% 50% tc tw(H) tw(L) tt 80% 20% tt Figure 5-4. System Oscillators DLPC7530 DLPS271 – APRIL 2024 www.ti.com 36 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: DLPC7530 |
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