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AD9995

–32–

AD9995

–33–

tPWR

tSYNC

1ST FIELD

CLOCKS ACTIVE WHEN OUT CONTROL

H2/H4

H1/H3, RG, DCLK

DIGITAL

OUTPUTS

(OUTPUT)

SYNC

(INPUT)

SERIAL

WRITES

CLI

(INPUT)

VDD

(INPUT)

Figure 35. Recommended Power-Up Sequence and Synchronization, Master Mode

POWER-UP AND SYNCHRONIZATION

Recommended Power-Up Sequence for Master Mode

When the AD9995 is powered up, the following sequence is

recommended (refer to Figure 35 for each step). Note that a

SYNC signal is required for Master mode operation. If an exter-

nal SYNC pulse is not available, it is also possible generate an

internal SYNC pulse by writing to the SYNCPOL register, as

described in the next section.

1. Turn on power supplies for AD9995.

2. Apply the master clock input CLI.

3. Reset the internal AD9995 registers by writing a 1 to the

SW_RESET register (Addr. 0x10 in Bank 1).

4. By default, the AD9995 is in Standby3 mode.To place the

part into normal power operation, write 0x004 to the AFE

OPRMODE register (Addr. 0x00 in Bank 1).

5. Write a 1 to the BANKSELECT register (Addr. 0x7F).

This will select Register Bank 2.

6. Load Bank 2 registers with the required VPAT group,

V-sequence, and field timing information.

7. Write a 0 to the BANKSELECT register to select Bank 1.

8. By default, the internal timing core is held in a reset state

with TGCORE_RSTB register = 0. Write a 1 to the TG-

CORE_RSTB register (Addr. 0x15 in Bank 1) to start the

internal timing core operation.

9. Load the required registers to configure the high speed tim-

ing, horizontal timing, and shutter timing information.

10. Configure the AD9995 for Master mode timing by writing a

1 to the MASTER register (Addr. 0x20 in Bank 1).

11. Write a 1 to the OUT_CONTROL register (Addr. 0x11 in

Bank 1). This will allow the outputs to become active after

the next SYNC rising edge.

12. Generate a SYNC event: If SYNC is high at power-up,

bring the SYNC input low for a minimum of 100 ns.

Then bring SYNC back high.This will cause the internal

counters to reset and will start VD/HD operation.The first

VD/HD edge allows most Bank 1 register updates to occur,

including OUT_CONTROL to enable all outputs.

Table XIII. Power-Up Register Write Sequence

Address

Data

Description

0x10

0x01

Reset All Registers to Default Values

0x00

0x04

Power Up the AFE and CLO Oscillator

0x7F

0x01

Select Register Bank 2

0x00–0xFF

VPAT,V-Sequence, and Field Timing

0x7F

0x00

Select Register Bank 1

0x15

0x01

Reset Internal Timing Core

0x30–71

Horizontal and Shutter Timing

0x20

0x01

Configure for Master Mode

0x11

0x01

Enable All Outputs after SYNC

0x13

0x01

SYNCPOL (for Software SYNC Only)

Generating Software SYNC without External SYNC Signal

If an external SYNC pulse is not available, it is possible to

generate an internal SYNC in the AD9995 by writing to the

SYNCPOL register (Addr. 0x13). If the software SYNC option is

used, the SYNC input (Pin 46) should be tied to ground (VSS).

After power-up, follow the same procedure as before for Steps

1 to 11.Then, for Step 12, instead of using the external SYNC

pulse, write a 1 to the SYNCPOL register.This will generate the

SYNC internally, and timing operation will begin.

REV. 0

AD9995 Datasheet(PDF) 33 Page - Analog Devices

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